MAX32665-MAX32668 User Guide
Maxim Integrated Page 439 of 457
You can save this extra ECC bit at the cost of an additional parity calculation. If the MSB of the data is set, the ECC parity bits
should be XOR’d with 2n+1-1 (n 1s). This effectively swaps the MSB of the data with the MSB of the ECC for purposes of
parity calculation. When examining the result, if the ECC calculation indicates the MSB of the data is corrupt (the result is
2n+1-1), then the error is really in the MSB of the ECC. If the result indicates the error is in the MSB of the ECC (the result is
2n+1), then the error is really in the MSB of the data.
ECC bits n and above are all identical. They all indicate the parity of the entire array. To use a block size of 64k bits (8k
bytes), the parity bit of the entire array (bit 16) can be duplicated to obtain the higher-order ECC bits.
You can generate Hamming codes over larger blocks using software. After the Hamming code is generated for an 8k block
of data, software should examine the parity of the block of data just calculated (bit 16 of the ECC register). If the parity of
the block is odd (parity bit is set), software should XOR additional software-maintained ECC bits with the inverse of the
block address. If the parity of the block is even (parity bit of the block is clear), software does not need to modify the
additional ECC bits. You should reset the parity of the block (bit 16 of the ECC register) for each block, but the remaining
ECC bits (B0-B15) should remain unchanged and accumulate their respective XORs throughout the entire array.
To achieve Double Error Detection (but not correction), include another ECC parity bit. If the result of the ECC XOR is not
zero, then this extra ECC bit should also be set indicating an error has occurred. If this bit is clear after the ECC XOR
operation, it means an even number of errors has occurred, and the data is not correctable. This does not mean this extra
ECC bit detects an even number of bit errors. It just indicates that an even number of errors have occurred. It is possible for
an even number of bit errors to masquerade as valid data. This extra ECC bit is capable of detecting two-bit errors. If an odd
number of bit errors occur, they always masquerade as a single correctable bit error. This is a limitation of using parity to
indicate error. Parity can only detect an odd number of errors. For stronger error detection, a Cyclic Redundancy Check
(CRC) is used.
The lower n ECC bits (B0 to Bn-1) are all that is needed to determine the location of a single-bit error in the data. The next
ECC bit (which is the parity of the entire array) is simply used to indicate there is an error in the data that needs to be
corrected. Subsequent ECC bits are only needed to detect an error in this added ECC bit or to detect double-bit errors. If an
alternative error detection scheme is used, such as a CRC, then only n ECC bits are needed to find the location of a single-bit
error in the data array.
Because all CRCs with at least two terms in the generator polynomial will detect all single-bit errors, ECC bit n, which is used
to determine if there is a single-bit error in the array by checking parity is unnecessary. A CRC polynomial with an even
number of terms has the parity polynomial (x+1) as one of its factors and checks parity as well. A CRC of sufficient length is
also capable of detecting all two-bit errors, making an ECC bit added for double-error detection unnecessary as well.
Because a single-bit error in the CRC is catastrophic, the CRC should also be protected with ECC bits. If the CRC is appended
to the data for the Hamming code calculation, you can protect it with the same set of ECC bits used to protect the data by
including one additional ECC bit to account for the increase in block size.
Most manufacturers of NAND Flash memories have application notes that describe the calculation of a variation of
Hamming codes. These application notes calculate parity on both the odd and even halves of the bit groups. As a result,
they require 2*n ECC bits, almost twice as many as necessary. If the even half is XOR’d with the odd half, the result is the
parity of the entire array. Instead of storing parity for both the even halves and odd halves of all bit groups (which requires
2*n ECC bits), an implementation only really needs to store the parity of the entire array (n+1 ECC bits). You can determine
the odd half of ECC bits by XORing the even half of ECC bits with the parity of the entire array. The parity of the entire array
is just the next bit in the ECC register, so saving n+1 bits from this register saves the parity of the entire array. Storing both
the odd and even parity halves offers no more error protection than the methods described above. For both methods, an
odd number of errors masquerades as a correctable single-bit error, and all double-bit errors are detected.
23.6 Modular Arithmetic Accelerator
The Modular Arithmetic Accelerator (MAA) is a dedicated hardware module that performs high-speed calculations that are
key parts of asymmetric cryptographic algorithms based on DSA, RSA, and ECDSA algorithms.
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