Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 105 of 457
Peripheral Clock Disable 1
GCR_PCLK_DIS1
[0x0048]
Bits
Field
Access
Reset
Description
0
btle
R/W
1
Bluetooth Digital Baseband Clock Disable
Disabling the clock disables functionality while also saving power. Associated register
states are retained but read and write access is blocked.
0: Enabled.
1: Disabled.
Table 4-65: Event Enable Register
Event Enable
GCR_EVENT_EN
[0x004C]
Bits
Field
Access
Reset
Description
31:6
-
RO
0
Reserved
Do not modify this field.
5
cpu1txevent
R/W
0
CPU1 TXEV On SEV Enable
When set, an SEV (Send Event) instruction causes a TXEV event from either CPU0 or
CPU1 to cause an RXEV event to wake CPU1 from a low power mode entered with a
WFE instruction.
0: Disabled.
1: Enabled.
4
cpu1dma1eve
nt
R/W
0
CPU1 DMA1 CTZ Wake-Up Enable
Allows a DMA1 CTZ event to generate an RXEV to wake-up CPU1 from a low power
mode entered with a WFE instruction.
0: Disabled.
1: Enabled.
3
cpu1dma0eve
nt
R/W
0
CPU1 DMA0 CTZ Wake-Up Enable
Allows a DMA0 CTZ event to generate an RXEV to wake-up CPU1 from a low power
mode entered with a WFE instruction.
0: Disabled.
1: Enabled..
2
cpu0txevent
R/W
0
CPU0 TXEV On SEV Enable
When set, an SEV (Send Event) instruction causes a TXEV event from either CPU0 or
CPU1 to cause an RXEV event to wake CPU1 from a low power mode entered with a
WFE instruction.
0: Disabled.
1: Enabled.
1
cpu0dma1eve
nt
R/W
0
CPU0 DMA1 CTZ Wake-Up Enable
Allows a DMA1 CTZ event to generate an RXEV to wake-up CPU0 from a low power
mode entered with a WFE instruction.
0: Disabled.
1: Enabled.
0
cpu0dma0eve
nt
R/W
0
CPU0 DMA0 CTZ Wake-Up Enable
Allows a DMA0 CTZ event to generate an RXEV to wake-up CPU0 from a low power
mode entered with a WFE instruction.
0: Disabled.
1: Enabled.

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English