MAX32665-MAX32668 User Guide
Maxim Integrated Page 274 of 457
13.1 I
2
C Master/Slave Features
Each I
2
C Master/Slave is compliant with the I
2
C Bus Specification and include the following features:
• Communicates via a serial data bus (SDA) and a serial clock line (SCL)
• Operates as either a master or slave device as a transmitter or receiver
• Supports I
2
C Standard Mode, Fast Mode, Fast Mode Plus and High Speed (Hs) mode
• Transfers data at rates up to:
100kbps in Standard Mode
400kbps in Fast Mode
1Mbps in Fast Mode Plus
3.4Mbps in Hs Mode
• Supports multi-master systems, including support for arbitration and clock synchronization for Standard, Fast and
Fast Plus modes
• Supports 7- and 10-bit addressing
• Supports RESTART condition
• Supports clock stretching
• Provides transfer status interrupts and flags
• Provides DMA data transfer support
• Supports I
2
C timing parameters fully controllable via firmware
• Provides glitch filter and Schmitt trigger hysteresis on SDA and SCL
• Provides control, status, and interrupt events for maximum flexibility
• Provides independent 8-byte RX FIFO and 8-byte TX FIFO
• Provides TX FIFO preloading
• Provides programmable interrupt threshold levels for the TX and RX FIFO
13.2 Instances
The three instances of the peripheral are shown in Figure 12-1: UART Frame Diagram. Table 13-1: MAX32665 – MAX32668
I2C Peripheral Pins lists the locations of the SDA and SCL signals for each of the I2Cn peripherals per package.
Table 13-1: MAX32665 – MAX32668 I
2
C Peripheral Pins
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