Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 227 of 457
9.3 Usage
Use the following procedure to perform a DMA transfer from a peripheral’s receive FIFO to memory, from memory to a
peripheral’s transmit FIFO, or from memory to memory.
1. Ensure DMACHn_CFG.chen, DMACHn_CFG.rlden = 0, and DMACHn_ST.ctz_st = 0.
2. If using memory for the destination of the DMA transfer, configure DMACHn_DST to the starting address of the
destination in memory.
3. If using memory for the source of the DMA transfer, configure DMACHn_SRC to the starting address of the source
in memory.
4. Write the number of bytes to transfer to the DMACHn_CNT register.
5. Configure the following DMACHn_CFG register fields in one or more instructions. Do not set DMACHn_CFG.chen to
1 or DMAn_CNT_RLD.rlden to 1 in this step:
a. Configure DMACHn_CFG.req_sel to select the transfer operation associated with the DMA channel.
b. Configure DMACHn_CFG.burst for the desired burst size.
c. Configure DMACHn_CFG.priority to set the channel priority relative to other DMA channels.
d. Configure DMACHn_CFG.dst_width to dictate the number of bytes written in each transaction.
e. If desired, set DMACHn_CFG.dst_inc to 1 to enable automatic incrementing of the DMACHn_DST register upon
every AHB transaction.
f. Configure DMACHn_CFG.src_width to dictate the number of bytes read in each transaction.
g. If desired, set DMACHn_CFG.src_inc to 1 to enable automatic incrementing of the DMACHn_DST register upon
every AHB transaction.
h. If desired, set DMACHn_CFG.chd_ien = 1 to generate an interrupt when the channel becomes disabled. The
channel becomes disabled when the DMA transfer completes or a bus error occurs.
i. If desired, set DMACHn_CFG.ctz_ien 1 to generate an interrupt when the DMACHn_CNT register is
decremented to zero.
6. If using the reload feature, configure the reload registers to set the destination, source, and count for the following
DMA transaction.
a. If desired, enable the channel timeout feature described in Channel Timeout Detect. Clear
DMACHn_CFG.to_prescale to 0x0 to disable the channel timeout feature.
7. Set DMAn_CNT_RLD.rl_den to 1 to enable the reload feature.
8. Set DMACHn_CFG.ch_en = 1 to immediately start the DMA transfer.
9. Wait for the status bit to become 0 to indicate the completion of the DMA transfer.
9.4 Count-To-Zero (CTZ) Condition
When an AHB channel burst completes, a CTZ condition exists if DMACHn_CNT is decremented to 0.

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English