Maxim Integrated MAX32665 - DMA Channel Register Details; Table 9-11: Dmachn Configuration Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 233 of 457
9.13 DMA Channel Register Details
Table 9-11: DMACHn Configuration Register
DMA Channel n Configuration
DMACHn_CFG
[0x0100]
Bits
Field
Access
Reset
Description
31
ctzien
R/W
0
CTZ Interrupt Enable
0: Disabled
1: Enabled. DMACn_INT.ipend is set to 1 whenever a CTZ event occurs.
30
chdien
R/W
0
Channel Disable Interrupt Enable
0: Disabled
1: Enabled. DMACn_INT.ipend bit is set to 1 whenever DMACHn_ST.ch_st
changes from 1 to 0.
29
-
RO
0
Reserved
28:24
brst
R/W
0
Burst Size
The number of bytes transferred into and out of the DMA FIFO in a single burst.
0b00000: 1 byte
0b00001: 2 bytes
0b00010: 3 bytes
...
0b11111: 32 bytes
23
-
RO
0
Reserved
22
distinc
R/W
0
Destination Increment Enable
This bit enables the automatic increment of the DMACHn_DST register upon
every AHB transaction. This bit is ignored for a DMA transmit to peripherals.
0: Disabled
1: Enabled
21:20
dstwd
R/W
0
Destination Width
Indicates the width of each AHB transaction to the destination peripheral or
memory (the actual width might be less than this if there are insufficient bytes in
the DMA FIFO for the full width).
0x0: One byte
0x1: Two bytes
0x2: Four bytes
0x3: Reserved
19
-
RO
0
Reserved
18
srinc
R/W
0
Source Increment on AHB Transaction Enable
This bit enables the automatic increment of the DMACHn_SRC register upon
every AHB transaction. This bit is ignored for a DMA receive from peripherals.
0: Disabled
1: Enabled
17:16
srcwd
R/W
0
Source Width
Indicates the width of each AHB transaction from the source peripheral or
memory. The actual width might be less than this if the DMACHn_CNT register
indicates a smaller value.
0x0: One byte
0x1: Two bytes
0x2: Four bytes
0x3: Reserved