MAX32665-MAX32668 User Guide
Maxim Integrated Page 93 of 457
GPIO Wakeup Enable
Activity on any GPIO pin configured for wakeup causes an exit from SLEEP,
DEEPSLEEP, and BACKUP modes.
0: Disabled.
1: Enabled.
Reserved
Do not modify this field.
Operating Mode
0b000: ACTIVE
0b010: DEEPSLEEP
0b011: Reserved.
0b100: BACKUP
Note: All other values are Reserved.
Table 4-58: Peripheral Clock Divisor Register
Peripheral Clocks Divisor
Reserved
Do not modify this field.
Always-on Domain (AoD) Clock Divider
Configures the frequency of the Always On Domain clock as shown in the
following equation.
Note: aondiv valid values are 0, 1, 2 and 3.
ADC Clock Divider
Configures the frequency of the ADC peripheral from the PCLK.
0x0: Reserved
0x1: Reserved
0x2 – 0xF:
Reserved
Do not modify this field.
SDHC Clock Frequency
Configures the frequency of the SDHC as a divisor of the 96MHz high-speed
oscillator.
0:
1:
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