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Maxim Integrated MAX32665 User Manual

Maxim Integrated MAX32665
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MAX32665-MAX32668 User Guide
Maxim Integrated Page 302 of 457
I2C Transmit Control 0
I2Cn_TX_CTRL0
[0x0024]
Bits
Field
Access
Reset
Description
2
gcamtxafdis
R/W
0
TX FIFO General Call Address Match Auto Flush Disable
Various situations or conditions are described in this user guide that lead to the
Transmit FIFO being flushed and locked out (I2Cn_INT_FL0.txloi = 1).
0: Enabled.
1: Disabled.
Note: upon entering TX Preload Mode, hardware will automatically set this bit to 1
Software can subsequently set to any value desired (ie HW does not
continuously force the bitfield to this value).
1
txfifordy
R/W
0
TX FIFO Ready Manual Mode
0: HW will control I2Cn_TX_CTRL1.txrdy
1: SW control of I2Cn_TX_CTRL1.txrdy
0
txpreld
R/W
0
TX FIFO Preload Mode Enable
0: Normal operation. An address match in Slave Mode, or a General Call address
match, will flush and lock the TX FIFO so it cannot be written and set
I2Cn_INT_FL0.txloi.
1: TX FIFO Preload Mode. An address match in Slave Mode, or a General Call
address match, will not lock the TX FIFO and will not set I2Cn_INT_FL0.txloi.
This allows firmware to preload data into the TX FIFO. The status of the I
2
C is
controllable at I2Cn_TX_CTRL1.txrdy.
Table 13-16: I
2
C Transmit Control 1 Register
I2C Transmit Control Register 1
I2Cn_TX_CTRL1
[0x0028]
Bits
Field
Access
Reset
Description
31:12
-
RO
0
Reserved
11:8
txfifo
R
0
Transmit FIFO Byte Count Status
0: No data in the TX FIFO.
1: 1 byte in the TX FIFO.
2: 2 bytes in the TX FIFO.
3: 3 bytes in the TX FIFO.
4: 4 bytes in the TX FIFO.
5: 5 bytes in the TX FIFO.
6: 6 bytes in the TX FIFO.
7: 7 bytes in the TX FIFO.
8: 8 bytes in the TX FIFO (max value).
7:1
-
RO
0
Reserved
0
txrdy
R/1
1
Transmit FIFO Preload Ready Status
When TX FIFO Preload Mode is enabled, I2Cn_TX_CTRL0.txpreld = 1, this bit is
automatically cleared to 0. While this bit is 0, if the I
2
C hardware receives a slave
address match a NACK is sent. Once the I
2
C hardware is ready (firmware has
preloaded the TX FIFO, configured the DMA, etc.) application firmware must set this
bit to 1 so the I
2
C hardware will send an ACK on a slave address match.
When TX FIFO Preload Mode is disabled, I2Cn_TX_CTRL0.txpreld = 1, this bit is
forced to 1 and the I
2
C hardware behaves normally.
Table 13-17: I
2
C Data Register
I2C Data
I2Cn_FIFO
[0x002C]
Bits
Field
Access
Reset
Description
31:8
-
RO
0
Reserved

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Maxim Integrated MAX32665 Specifications

General IconGeneral
BrandMaxim Integrated
ModelMAX32665
CategoryMotherboard
LanguageEnglish