Maxim Integrated MAX32665 - Table 8-90: SDHC ADMA System Address Register 1; Table 8-91: Preset Value Register Example; Table 8-92: Preset Value Register Selection Conditions

MAX32665-MAX32668 User Guide
Maxim Integrated Page 219 of 457
Table 8-90: SDHC ADMA System Address Register 1
ADMA System Address Register 1
SDHC_ADMA_ADDR_1
[0x005C]
Bits
Name
Access
Reset
Description
31:0
addr
R/W
0
ADMA System Address 1
Most-significant word for the 64-bit ADMA address. See SDHC_ADMA_ADDR_0 for
details.
8.5.6.4 Preset Value Registers
All Preset Value registers (SDHC_PRESET_0 to SDHC_PRESET_7) contain the same fields as described in the SDHC_PRESET_0
register. One of the Preset Value registers is automatically selected by the SDHC based on the selected bus-speed mode
Table 8-91 shows a group of preset values per card or device. One of the Preset Value registers (SDHC_PRESET_1 –
SDHC_PRESET_7) is selected by the SDHC hardware based on the Selected Bus Speed mode. Table 8-92 defines the
conditions to select one of the Preset Value registers.
Table 8-91: Preset Value Register Example
Offset
Preset Value Registers
Signal Voltage
[0x0060]
Preset Value for Initialization
3.3V or 1.8V
[0x0062]
Preset Value for Default Speed
3.3V
[0x0064]
Preset Value for High Speed
3.3V
[0x0066]
Preset Value for SDR12
1.8V
[0x0068]
Preset Value for SDR25
1.8V
[0x006A]
Preset Value for SDR50
1.8V
[0x006C]
Preset Value for SDR104
1.8V
[0x006E]
Preset Value for DDR50
1.8V
Table 8-92: Preset Value Register Selection Conditions
Selected Bus
Speed Mode
1.8V Signaling Enable
SDHC_HOST_CN_2. 1_8v_signal
High Speed Enable
SDHC_HOST_CN_1. hs_en
UHS-I Mode Selection
SDHC_HOST_CN_2.uhs
Default Speed
0
0
N/A
High Speed
0
1
N/A
SDR12
1
N/A
0b000
SDR25
1
N/A
0b001
SDR50
1
N/A
0b010
SDR104
1
N/A
0b011
DDR50
1
N/A
0b100
Reserved
1
N/A
0b101 to 0b111