MAX32665-MAX32668 User Guide
Maxim Integrated Page 41 of 457
3.4.2 AHB Masters
3.4.2.1 USB Endpoint Buffer Manager
The USB AHB bus master is used to manage endpoint buffers in the SRAM. It has access to the SRAM (read/write, for
storage and retrieval of endpoint buffer data), as well as the internal and/or external flash data contents (which can be
used to contain static data for transmission by the USB).
3.4.2.2 Standard DMA
The Standard DMA bus master has access to all off-core memory areas accessible by the System bus. It does not have
access to the Arm Private Peripheral Bus area.
3.4.2.3 SDHC
The SDHC bus master has access to all off-core memory areas accessible by the System bus. It does not have access to the
Arm Private Peripheral Bus area.
3.4.2.4 Trust Protection Unit (TPU)
The TPU bus master has access to all off-core memory areas accessible by the System bus. It does not have access to the
Arm Private Peripheral Bus area.
3.5 Peripheral Register Map
3.5.1 APB Peripheral Base Address Map
Table 3-1, below, contains the base address for each of the APB mapped peripherals. The base address for a given
peripheral is the start of the register map for the peripheral. For a given peripheral, the address for a register within the
peripheral is defined as the APB peripheral base address plus the registers offset.
Table 3-1: APB Peripheral Base Address Map
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