MAX32665-MAX32668 User Guide
Maxim Integrated Page 306 of 457
14. Quad Serial Peripheral Interface (SPI)
The Quad Serial Peripheral Interface (QSPI) is a highly configurable, flexible, and efficient synchronous interface between
multiple SPI devices on a single bus. The SPI bus uses a single clock signal, single, dual or quad data lines, and one or more
slave select lines for communication with external SPI devices. An SPI network uses a single master and one or more slaves
for any given transaction.
The provided QSPI ports support full-duplex, bi-direction I/O and each QSPI includes a Bit Rate Generator (BRG) for
generating the clock signal when operating in master mode. Each QSPI port operates independently and requires minimal
processor overhead. All instances of the SPI peripheral support both master and slave modes, and support single master
and multi-master networks.
Features include:
• Dedicated Bit Rate Generator for precision serial clock generation in Master Mode
Up to
for instances on the APB bus
Up to
for instances on the AHB bus
Programmable SCK duty cycle timing
• Full-duplex, synchronous communication of 1 to 16-bit characters
• 3-wire and 4-wire SPI operation for single-bit communication
• Single, Dual and Quad I/O
• Byte-wide Transmit and Receive FIFOs with 32-byte depth
For character sizes greater than 8, each character uses 2 entries per character resulting in 16 entries for the
Transmit and Receive FIFO
• Transmit and Receive DMA support
• SPI modes 0, 1, 2, 3
• Configurable slave select lines
Programmable slave select level
• Programmable slave select timing with respect to SCK starting edge and ending edge
• Multi-master mode fault detection
Figure 14-1: QSPI Block Diagram shows the structure of the peripheral. See Table 14-1: MAX32665—MAX32668 SPI
Instances for the peripheral-specific peripheral bus assignment and bit rate generator clock source.
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