Maxim Integrated MAX32665 - Table 11-10: ADC Limit 0 to 3 Registers

MAX32665-MAX32668 User Guide
Maxim Integrated Page 258 of 457
ADC Interrupt Control
ADC_INTR
[0x000C]
Bits
Field
Access
Reset
Description
18
adc_hi_limit_if
R/W1C
0
ADC High Limit Interrupt Flag
1: The last conversion resulted in a high-limit condition for one of the limit
registers.
17
ref_ready_if
R/W1C
0
ADC Reference Ready Interrupt Flag
0: Not Ready
1: Ready.
16
done_if
R/W1C
0
ADC Conversion Complete Interrupt Flag
Set by the ADC hardware when an ADC conversion is complete.
1: ADC conversion complete
15:5
-
RO
0
Reserved for Future Use
Do not modify this field.
4
overflow_ie
R/W
0
ADC Overflow Interrupt Enable
0: Disabled.
1: Enables interrupt assertion when hardware sets ADC_INTR.overflow_if.
3
adc_lo_limit_ie
R/W
0
ADC Low Limit Interrupt Enable
0: Disabled.
1: Enables interrupt assertion when hardware sets the ADC_INTR.lo_limit_if.
2
adc_hi_limit_ie
R/W
0
ADC High Limit Interrupt Enable
0: Disabled.
1: Enables interrupt assertion when hardware sets ADC_INTR.lo_limit_if.
1
ref_ready_ie
R/W
0
ADC Reference Ready Interrupt Enable
0: Disabled.
1: Enables interrupt assertion when hardware sets ADC_INTR.ref_ready_if.
0
done_ie
R/W
0
ADC Conversion Complete
0: Disabled.
1: Enables interrupt assertion when hardware sets ADC_INTR.done_if.
Table 11-10: ADC Limit 0 to 3 Registers
ADC Limit 0
ADC_LIMIT0
[0x0010]
ADC Limit 1
ADC_LIMIT1
[0x0014]
ADC Limit 2
ADC_LIMIT2
[0x0018]
ADC Limit 3
ADC_LIMIT3
[0x001C]
Bits
Field
Access
Reset
Description
31:30
-
RO
0
Reserved for Future Use
Do not modify this field.
29
ch_hi_limit_en
R/W
0
High Limit Monitoring Enable
If set, then an ADC conversion that results in a value greater than the ch_high_limit
field generates an ADC interrupt if the ADC high-limit interrupt is enabled.
(ADC_INTR.hi_limit_ie = 1).
1: The high-limit comparison for the ch_sel channel is active.
0: The high-limit comparison is not enabled.
28
ch_lo_limit_en
R/W
0
Low Limit Monitoring Enable
If set, then an ADC conversion that results in a value less than the ch_high_limit
field generates an ADC interrupt if the ADC low-limit interrupt is enabled
(ADC_INTR.lo_limit_ie = 1).
1: The low-limit comparison for the ch_sel channel is active.
0: The low-limit comparison is not enabled.
27:24
ch_sel
R/W
0
ADC Channel for Limit Monitoring
Sets the ADC input channel for high- and low-limit thresholds. See ADC_CTRL 
for valid values for this field.