Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 164 of 457
SPIXFM Fetch Control Register
SPIXFM_FETCH_CTRL
[0x0004]
Bits
Name
Access
Reset
Description
15:14
-
R/W
0
Reserved for Future Use
Do not modify this field.
13:12
data_width
R/W
0
Data Width
Number of data I/O used to receive data.
0b00: Single SDIO
0b01: Dual SDIO
0b10: Quad SDIO
0b11: Reserved
11:10
addr_width
R/W
0
Address Width
Number of data I/O used to send address and mode/dummy clocks.
0b00: Single SDIO
0b01: Dual SDIO
0b10: Quad SDIO
0b11: Reserved
9:8
cmdwth
R/W
0
Command Width
Number of data I/O used to send commands.
0b00: Single SDIO
0b01: Dual SDIO
0b10: Quad SDIO
0b11: Reserved
7:0
cmdval
R/W
0
Command Value
Command value sent to target to initiate fetching from SPI flash.
Table 8-18. SPIXFM Mode Control Register
SPIXFM Mode Control Register
SPIXFM_MODE_CTRL
[0x0008]
Bits
Name
Access
Reset
Description
31:10
-
R/W
0
Reserved for Future Use
Do not modify this field.
9
mode_send
R/W
0
Mode Send
Setting this field ensures that the next SPI flash transaction will send the mode
byte as defined in the SPIXFM_MODE_DATA.mddata field.
When this field is set, the next SPI flash read operation exits continuous mode
cleanly. This field and the SPIXFM_MODE_CTRL.nocmd field is automatically
cleared by hardware after the next SPI transaction.
0: No Action.
1: Send Mode Byte on next transaction
8
nocmd
R/W
0
No Command Mode
Read command sent only once after this bit is set.
0: Send read command every time SPI transaction is initiated.
1: Send read command on first transaction only and not on subsequent
transactions.
7:4
-
R/W
0
Reserved for Future Use
Do not modify this field.

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English