Maxim Integrated MAX32665 - Table 8-7. SPIXF Controller General Control Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 153 of 457
Table 8-7. SPIXF Controller General Control Register
SPIXF Controller General Control Register
SPIXFC_GEN_CTRL
[0x0008]
Bits
Name
Access
Reset
Description
31:26
-
R/W
0
Reserved for Future Use
Do not modify this field.
25
sckfbinv
R/W
0
SCK Inversion
0: Use SCK as feedback clock
1: Use inverted SCK as feedback clock
24
sckfb
R/W
0
Enable SCK Feedback mode
0: Disable SCK feedback mode.
1: Enable SCK feedback mode.
23
-
R/W
0
Reserved for Future Use
Do not modify this field.
22
smplss
R/W
0
Simple Mode Slave Select
0: No action
1: Deassert Slave Select when simple = 1
21
simplerx
R/W
0
Simple Receive Enable
Setting this bit to a 1 initiates a SPI transaction as defined in the Receive-Only
Transaction Header when in Simple Mode.
0: No action
1: Initiate SPI transaction
20
simple
R/W
0
Simple Mode Enable
0: Simple Mode disabled
1: Simple Mode enabled
19:16
bbdatoe
R/W
0
Bit Bang SDIO Output Enable
Enable output of SDIO0-3 in Bit-Bang mode.
bit3 = SDIO[3]
bit2 = SDIO[2]
bit1 = SDIO[1]
bit0 = SDIO[0]
15:12
bbdat
R/W
0
SDIO Drive value in Bit-Bang mode
Defines the output state of the SDIO outputs when in Bit-Bang mode
(SPIXFC_GEN_CTRL.bbmode=1)
bit[3]: SDIO[3]
bit[2]: SDIO[2]
bit[1]: SDIO[1]
bit[0]: SDIO[0]
11:8
sdatain
R/W
-
SDIO Input Data Value
Returns the state of the SDIO Input values. Writes to this field have no effect.
bit3: SDIO[3]
bit2: SDIO[2]
bit 1: SDIO[1]
bit 0: SDIO[0]
7
-
R/W
0
Reserved for Future Use
Do not modify this field.