MAX32665-MAX32668 User Guide
Maxim Integrated Page 425 of 457
Early DMA OUT Endpoints Enable
0: DMA Request signal for all OUT endpoints is deasserted when
USBHS_INMAXP bytes have been read from an endpoint.
1: DMA Request signal for all OUT endpoints is deasserted when
bytes have been read from an endpoint.
Table 21-32: USBHS Hi-Speed Chirp Timeout Register
USBHS Hi-Speed Chirp Timeout
HS Chirp Timeout Clock Cycles
This configures the chirp timeout used by this Device to negotiate a HS connection
with a FS Host.
The timeout value represents the number of 30MHz PHY clock cycles (66.7ns) before
the chirp timeout occurs.
Table 21-33: USBHS Hi-Speed RESUME Delay Register
USBHS Hi-Speed RESUME Delay
Hi-Speed RESUME Delay Clock Cycles
This configures the delay from when the RESUME state on the bus ends, to when the
USBHS resumes normal operation.
The delay value represents the number of 30MHz PHY clock cycles (66.7ns) from the
end of the RESUME state to when normal USBHS operation begins.
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