Maxim Integrated MAX32665 - Table 8-74: Transfer Complete and Data Timeout Error Priority and Status; Table 8-75: Command Complete and Command Timeout Error Priority and Status; Table 8-76: SDHC Error Interrupt Status Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 205 of 457
Table 8-74: Transfer Complete and Data Timeout Error Priority and Status
Transfer Complete
SDHC_INT_STAT.trans_comp
Data Timeout Error
SDHC_ER_INT_STAT.data_to
Status
0
0
Interrupted by another event
0
1
Timeout occurred during transfer
1
N/A
Command execution complete
Table 8-75: Command Complete and Command Timeout Error Priority and Status
Transfer Complete
SDHC_INT_STAT.cmd_comp
Data Time Error
SDHC_ER_INT_STAT.cmd_to
Status
0
0
Interrupted by another event.
N/A
1
Response not received within 64 SD Clock cycles.
1
0
Response received.
8.5.6.2 Error Interrupt Status Register
The interrupts defined in this register are enabled by the corresponding fields in the Error Interrupt Status Enable
(SDHC_ER_INT_EN) register. Setting any field in the SDHC_ER_INT_SIGNAL register enables SDHC error interrupt generation
using the SDHC_IRQ. The interrupt occurs when any field in the SDHC_ER_INT_STAT register is set to 1.
Table 8-76: SDHC Error Interrupt Status Register
Error Interrupt Status Register
SDHC_ER_INT_STAT
[0x0032]
Bits
Name
Access
Reset
Description
15:13
-
R/W1C
0
Reserved for Future Use
Do not modify this field.
12
dma
R/W1C
0
DMA Error
Error in SDMA transaction
1: Error
0: No error
11:10
-
R/W1C
0
Reserved for Future Use
Do not modify this field.
9
adma
R/W1C
0
ADMA Error
Set when the SDHC detects an error during an ADMA data transfer. The state
of the ADMA when the error occurs is saved in the ADMA Error Status
(SDHC_ADMA_ER) register.
This bit is also set if the SDHC detects invalid descriptor data. If the
SDHC_ADMA_ER register indicates an ADMA Error State, then an invalid
descriptor was detected.
1: Error
0: No error