MAX32665-MAX32668 User Guide
Maxim Integrated Page 249 of 457
11.4 Clock Configuration
The ADC clock, adcclk, is controlled by the GCR_PCLK_DIV.adcfrq register field. Configure this field for the target ADC
sample frequency. The maximum clock supported by the ADC is 8MHz. The divisor selection, GCR_PCLK_DIV.adcfrq, for the
ADC depends on the peripheral clock. Equation 11-2 shows the calculation for the ADC clock frequency, where:
.
Equation 11-2: ADC Clock Frequency
The GCR_PCLK_DIV.adcfrq register field setting must result in a value for
as shown in Table 11-2 with the
System Clock set as the 96MHz high frequency oscillator.
Table 11-2: ADC Clock Frequency and ADC Conversion Time (
,
)
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