MAX32665-MAX32668 User Guide
Maxim Integrated Page 64 of 457
Perform the following steps to enable SFCC.
1. Set PWRSEQ_LPMEMSD.icachexipsd to 0 to ensure the cache power is on.
2. Set SFCC_CACHE_CTRL.enable to 1.
3. Read SFCC_CACHE_CTRL.ready until it returns 1.
4.5.2 Flushing the ICC0/ICC1/SFCC Cache
The System Configuration Register (GCR_SCON) includes a field for flushing these caches simultaneously. Setting
GCR_SCON.ccache_flush to 1 performs a flush of all three caches. Flush only one of the caches by invalidating the cache
contents. Setting the ICCn_INVALIDATE register to 1 invalidates the respective cache and forces a cache flush. Read the
ICCn_CACHE_CTRL.ready field until it returns 1 to determine when the flush is completed.
4.5.3 Flushing SRCC Cache
The System Configuration Register (GCR_SCON) includes a field for flushing this caches. Setting GCR_SCON.dcache_flush to
1 performs a flush of the cache.
4.6 Instruction Cache Controller Registers
See Table 3-1: APB Peripheral Base Address Map for the ICC0, ICC1, and SFCC, Peripheral Base Addresses.
Table 4-3: Instruction Cache Controller Register Summary
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