Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 165 of 457
SPIXFM Mode Control Register
SPIXFM_MODE_CTRL
[0x0008]
Bits
Name
Access
Reset
Description
3:0
mdclk
R/W
0
Mode Clocks
Number of SPI clocks needed during the mode/dummy phase of fetch.
Table 8-19. SPIXFM Mode Data Register
SPIXFM Mode Data Register
SPIXFM_MODE_DATA
[0x000C]
Bits
Name
Access
Reset
Description
31:16
mdoe
R/W
0
Mode Output Enable
Output enable state for each corresponding data bit in
SPIXFM_MODE_DATA.mddata.
0: Output enable off, I/O is tristate stated.
1: Output enable on, I/O is driving SPIXFM_MODE_DATA.mddata.
15:0
mddata
R/W
0
Mode Data
Specifies the data to send with the dummy/mode clocks.
Table 8-20. SPIXFM SCK Feedback Control Register
SPIXFM SCK Feedback Control Register
SPIXFM_FB_CTRL
[0x0010]
Bits
Name
Access
Reset
Description
31:2
-
R/W
0
Reserved for Future Use
Do not modify this field.
1
fbinv
R/W
0
SCK feedback Clock inversion.
The feedback clock can be phase selected to increase the timing margin for
input data from the slave external flash device.
0: Non-inverted SCK is used for feedback clock
1: Inverted SCK is used for feedback clock
0
fbmd
R/W
0
SCK Feedback Mode Enable. Enable SCK feedback mode
0: Disable SCK feedback mode
1: Enable SCK feedback mode
Table 8-21. SPIXFM I/O Control Register
SPIXFM I/O Control Register
SPIXFM_IO_CTRL
[0x001C]
Bits
Name
Access
Reset
Description
31:5
-
R/W
0
Reserved for Future Use
Do not modify this field.
4:3
pupdctrl
R/W
1
IO Pullup/Pulldown Control
These bits control the pullups and pulldowns associated with all SPIXF SDIO pins.
0b00: tristate
0b01: pullup
0b10: pulldown
0b11: pullup
2
sdio_ds
R/W
1
SDIO Drive Strength
This bit controls the drive strength of all SDIO pins.
0: Low Drive Strength.
1: Hi Drive Strength.

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English