MAX32665-MAX32668 User Guide
Maxim Integrated Page 319 of 457
Table 14-12: QSPIn Master Clock Configuration Registers
QSPIn Master Clock Configuration Register
Reserved for Future Use
Do not modify this field.
SPI Peripheral Clock Scale
Scales the QSPI input clock (PCLK for QSPI0/QSPI1 and HCLK for QSPI2) by 2scale to
generate the QSPIn peripheral clock.
Valid values for scale are 0 to 8 inclusive. Values greater than 8 are reserved for future
use.
Note: If QSPIn_CLK_CFG.scale = 0, QSPIn_CLK_CFG.hi = 0, and QSPIn_CLK_CFG.lo = 0,
character sizes of 2 and 10 bits are not supported.
SCK Hi Clock Cycles Control
0: Hi duty cycle control disabled. Only valid if scale = 0.
1 to 15: The number of QSPIn peripheral clocks,
, that SCK is high.
Note: If QSPIn_CLK_CFG.scale = 0, QSPIn_CLK_CFG.hi = 0, and QSPIn_CLK_CFG.lo = 0,
character sizes of 2 and 10 bits are not supported.
SCK Low Clock Cycles Control
This field controls the SCK low clock time and is used to control the overall SCK duty
cycle in combination with the QSPIn_CLK_CFG.hi field.
0: Low duty cycle control disabled. Setting this field to 0 is only valid if
QSPIn_CLK_CFG.scale = 0.
1 to 15: The number of QSPIn peripheral clocks,
, that the SCK signal is low.
Note: If QSPIn_CLK_CFG.scale = 0, QSPIn_CLK_CFG.hi = 0, and QSPIn_CLK_CFG.lo = 0,
character sizes of 2 and 10 bits are not supported.
Table 14-13: QSPIn DMA Control Registers
QSPIn DMA Control Register
RX DMA Enable
0: Disabled. Any pending DMA requests are cleared
1: Enabled
Reserved for Future Use
Do not modify this field.
Number of Bytes in the RX FIFO
Read returns the number of bytes currently in the RX FIFO
Clear the RX FIFO
1: Clear the RX FIFO and any pending RX FIFO flags in QSPIn_INTFL. This should
be done when the RX FIFO is inactive.
Writing a 0 has no effect.
RX FIFO Enabled
0: Disabled
1: Enabled
Reserved for Future Use
Do not modify this field.
To Next Page
Loading...
Need help?
General