MAX32665-MAX32668 User Guide
Maxim Integrated Page 62 of 457
To start a Soft Reset, set GCR_RST0.soft_rst = 1. The reset will be completed immediately upon setting
GCR_RST0.soft_rst = 1.
4.3.3 System Reset
This is the same as Soft Reset except it also resets all GCR, resetting the clocks to their default state. The CPU state is reset
as well as the watchdog timers. The AoD and RAM are unaffected.
A watchdog timer reset event initiates a System Reset. To start a System Reset from firmware, set GCR_RST0.sys_rst = 1.
4.3.4 Power-On Reset
A POR resets everything in the device to its default state.
4.4 Cache
Each of the four cache controllers are independently managed. Figure 4-6 MAX32665—MAX32668 Cache Controllers
Diagram shows the four cache controllers and their memory interfaces. Instruction Cache Controller 0 (ICC0 dedicated to
CPU0) and Instruction Cache Controller 1 (ICC1 dedicated to CPU1) and the SPIXF Cache Controller (SFCC) are used for
instruction caching only. ICC0 and ICC1 interfaces to the internal 1MB Flash and SFCC interfaces to an external SPI Flash
device for external code execution. The SPIXR Data Cache Controller (SRCC) is used for data and instruction caching for
external SPI SRAM memories. The SRCC is implemented as a write-through cache.
All four caches are managed separately using their specific cache controller, ICC0, ICC1, SFCC, SRCC. Each controller can be
enabled, disabled, and invalidated. Each cache clock can be disabled by placing it in LIGHTSLEEP.
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