MAX32665-MAX32668 User Guide
Maxim Integrated Page 35 of 457
Figure 3-1: Code Memory Mapping
Undefined
0x00 00_0000
0x0FFF_FFFF
I-Code A ccess to Code Space
(cach ed)
0x10 00_0000
0x1010_0000
Reserved
0x1FFF_FFFF
0x08 00_0000
0x07FF_FFFF
Executable SRAM
(Not cached)
0x20 00_0000
Reserved
0xFFFF_FFFF
I-Code A HB Bus Master
System AHB Bus Master (for code fetche s)
Legend
Arm Cortex-M4 Defined Buse s
Memory Spaces
Memory Spaces (Cached)
External Memory Device (Optional)
Intern al Memory Instances
0x3FFF_FFFF
I-Code Access to Code Sp ace
(cach ed)
0x60 00_0000
0x7FFF_FFFF
0x80 00_0000
0x9FFF_FFFF
Reserved
0xA000_0000
Undefined
0x4000_0000
0x5FFF_FFFF
External SPI Flash Memory
(QSPI SPIXF, 128MB Maximum)
Internal Program/Data Flash Memory
512KB (Block 0) + ECC
0x0FFF_FFFF
0x1000_0000
0x100F_FFFF
0x0800_0000
0x2000_0000
0x2008_BFFF
External SPI SRAM
(QSPI SPIXR, 512MB Maximum)
0x8000_0000
0x9FFF_FFFF
Undefined/Reserve d
0x1007_FFFF
0x1008_0000
Internal Program/Data Flash Memory
512KB (Block 1) + ECC
0x10 0F_FFFF
0x2008_BFFF
0x2008_C000
Reserved
SRAM
560KB (no ECC)
448KB (with ECC)
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