Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 307 of 457
Figure 14-1: QSPI Block Diagram
QSPI REGISTER AND
CONTROL INTERFACE
QSPIn _MOSI / SDIO0 / SOSI
BUS
INTERFACE**
QSPIn IRQ
RX DMA
REQUEST
QSPIn_SCK
QSPIn_SS0
TX DMA
REQUEST
QSPIn_SS1*
QSPIn_SS2*
QSPIn _MISO / SDIO1
QSPIn_SDIO2
QSPIn _SDIO3
BIT RATE
GENERATOR
BIT RATE
GENERATOR
CLOCK SOURCE
QSPIn_CTRL0.mm_en
QSPIn_SS3*
* The number of slave select signals varies can vary for each instance of the peripheral.
** The bus interface (APB or AHB) can vary for each instance of the peripheral.
I/O MODE
DECODER
16-BIT SHIFT
REGISTE R
16-BIT SHIFT
REGISTER
RECEIVE
FIFO
TRANSMIT
FIFO
QSPI
14.1 Instances
The following instances of the peripheral are provided. For a specific instance replace n in register names with either 0, 1, or
2 depending on the instance of the peripheral.
Table 14-1: MAX32665—MAX32668 SPI Instances
Name
Formats
Bus
Assignment
Bit Rate Generator
Clock Source
Frequency
Slave Select Signals
3-Wire
4-Wire
Dual
Quad data
109 WLP
121 CTBGA
SPI0
Yes
Yes
Yes
Yes
APB
f
PCLK
3
3
SPI1
Yes
Yes
Yes
Yes
APB
f
PCLK
3
3
SPI2
Yes
Yes
Yes
Yes
AHB
f
HCLK
3
3

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English