Maxim Integrated MAX32665 - Registers; Register Details; Table 11-5. ADC Registers Summary; Table 11-6: ADC Control Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 255 of 457
11.9 Registers
See Table 3-1: APB Peripheral Base Address Map for the base peripheral address of these registers. All fields are reset on
peripheral, system, or power-on reset events unless otherwise specified.
Table 11-5. ADC Registers Summary
Offset
Name
Description
[0x0000]
ADC_CTRL
ADC Control Register
[0x0004]
ADC_STATUS
ADC Status Register
[0x0008]
ADC_DATA
ADC Output Data Register
[0x000C]
ADC_INTR
ADC Interrupt Control Register
[0x0010]
ADC_LIMIT0
ADC Limit 0 Register
[0x0014]
ADC_LIMIT1
ADC Limit 1 Register
[0x0018]
ADC_LIMIT2
ADC Limit 2 Register
[0x001C]
ADC_LIMIT3
ADC Limit 3 Register
11.10 Register Details
Table 11-6: ADC Control Register
ADC Control
ADC_CTRL
[0x0000]
Bits
Field
Access
Reset
Description
31:21
-
RO
0x050
Reserved for Future Use
Do not modify this field.
20
data_align
R/W
0
ADC Data Alignment
Selects the alignment of the 16-bit data conversion stored in the DATA register.
0: Data is LSB justified in 16-bit DATA register. DATA[15:10] = 0.
1: Data is MSB justified in 16-bit DATA register. DATA[5:0] = 0.
19
-
RO
0
Reserved for Future Use
Do not modify this field.
18:17
adc_divsel
R/W
0
External Input Scale
Scales the external inouts AIN0-AIN7. All eight of external inputs are scaled by the
same value
0x0: No scaling.
0x1: Divide by 2
0x2: Divide by 3
0x3: Divide by 4