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Maxim Integrated MAX32665 User Manual
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MAX32665-MAX32668 User Guide
Maxim Integrated
Page
51
of
457
Figure 4-1: Clock Bloc
k Diagram
50
52
Table of Contents
Default Chapter
2
Table of Contents
2
1 Overview
24
Block Diagram
25
Figure 1-1: MAX32665-MAX32668 Block Diagram
25
2 Resource Protection Unit (RPU)
26
Instances
26
Table 2-1: Dual Mapped APB Peripherals
26
Table 2-2. MAX32665-MAX32668 Master Permission Bits
26
Table 2-3: MAX32665-MAX32668 AHB Slaves
27
Table 2-4. MAX32665-MAX32668 AHB Master/Slave Interconnect Matrix
27
Usage
28
Reset State
28
MPU Implementation
28
MPU Protection Fault
28
RPU Protection Fault
28
RPU Fault Handler
28
Registers
29
Table 2-5: RPU APB Register Offsets, Names, Access, and Descriptions
29
Table 2-6: RPU AHB Slave Register Addresses, Names, Access, and Descriptions
30
Register Details
31
Table 2-7: RPU APB Slave Permission Registers
31
Table 2-8: RPU AHB Slave Permission Register
33
3 Memory, Register Mapping, and Access
34
Memory, Register Mapping, and Access Overview
34
Figure 3-1: Code Memory Mapping
35
Figure 3-2: Data Memory Mapping
36
Standard Memory Regions
37
Code Space
37
SRAM Space
37
Peripheral Space
38
External RAM Space
38
External Device Space
39
System Area (Private Peripheral Bus)
39
System Area (Vendor Defined)
39
Device Memory Instances
39
Main Program Flash Memory
39
Cache Memories
39
External Memory Cache Controller (EMCC)
40
Information Block Flash Memory
40
System SRAM
40
AES Key and Working Space Memory
40
MAA Key and Working Space Memory
40
TPU Memory
40
AHB Interfaces
40
Core AHB Interfaces
40
AHB Masters
41
Peripheral Register Map
41
APB Peripheral Base Address Map
41
Table 3-1: APB Peripheral Base Address Map
41
AHB Peripheral Base Address Map
42
Error Correction Coding (ECC) Module
43
Sram
43
Flash
43
Cache
43
Limitations
43
Table 3-2: AHB Peripheral Base Address Map
43
Table 3-3: Error Correction Coding (ECC) Enable Register
44
Table 3-4: Error Correction Coding (ECC) Error Register
44
Table 3-5: Correctable Error Detected Register
46
Table 3-6: Error Correction Coding (ECC) Interrupt Enable Register
47
Table 3-7: Error Correction Coding (ECC) Address Register
48
4 System, Power, Clocks, Reset
50
Oscillator Sources and Clock Switching
50
Figure 4-1: Clock Block Diagram
51
32Mhz Bluetooth Radio Oscillator
52
60Mhz Low Power Internal Oscillator
52
96Mhz Internal Main High-Speed Oscillator
52
Oscillator Inplementation
52
8Khz Ultra-Low Power Nano-Ring Internal Oscillator
53
8Mhz Internal Oscillator
53
Figure 4-2: Example 32Mhz Crystal Capacitor Determination
53
Khz External Crystal Oscillator
53
Operating Modes
54
ACTIVE Mode
54
SLEEP Low Power Mode
54
Table 4-1: Wakeup Sources
54
Figure 4-3: SLEEP Mode Clock Control
55
DEEPSLEEP Low Power Mode
56
Figure 4-4: DEEPSLEEP Clock Control
57
BACKUP Low Power Mode
58
Figure 4-5: BACKUP Mode Clock Control
59
Device Resets
60
Table 4-2: Reset and Low Power Mode Effects
60
Peripheral Reset
61
Soft Reset
61
Power-On Reset
62
System Reset
62
Cache
62
Instruction Cache Controller
63
Enabling ICC0/ICC1/SFCC
63
Figure 4-6: MAX32665-MAX32668 Cache Controllers Control
63
Flushing the ICC0/ICC1/SFCC Cache
64
Flushing SRCC Cache
64
Instruction Cache Controller Registers
64
Table 4-3: Instruction Cache Controller Register Summary
64
Table 4-4: SPIXF Cache Controller Register Summary
64
Table 4-5: Iccn Cache ID Register
64
Table 4-6: Iccn Memory Size Register
65
Table 4-7: Iccn Cache Control Register
65
Table 4-8: Iccn Invalidate Register
65
Table 4-9: SFCC Cache ID Register
65
External RAM SPIXR Cache Controller (SRCC)
66
Table 4-10: SFCC Memory Size Register
66
Table 4-11: SFCC Cache Control Register
66
Table 4-12: SFCC Invalidate Register
66
RAM Memory Management
67
RAM Zeroization
67
RAM Low Power Modes
67
Table 4-13 RAM Block Size and Base Address
67
Miscellaneous Control Registers
68
Miscellaneous Control Registers Details
68
Table 4-14 Miscellaneous Control Register Summary
68
Table 4-15: Error Correction Coding (ECC) Enable Register
68
Table 4-16: SQWOUT and PDOWN Output Enable Register
69
Table 4-17: Comparator Enable Register
69
Table 4-18: Control Register
70
Single Inductor Multiple Output (SIMO) Power Supply
71
Power Supply Monitor
71
Table 4-19: SIMO Power Supply Device Pin Connectivity
71
Single Inductor Multiple Output (SIMO) Registers
72
Table 4-20: SIMO Controller Register Summary
72
Single Inductor Multiple Output (SIMO) Registers Details
73
Table 4-21: Buck Voltage Regulator a Control Register
73
Table 4-22: Buck Voltage Regulator B Control Register
73
Table 4-23: Buck Voltage Regulator C Control Register
74
Table 4-24: Buck Voltage Regulator D Control Register
74
Table 4-25: High Side FET Peak Current VREGO_A VREGO_B Register
74
Table 4-26: High Side FET Peak Current VREGO_C VREGO_D Register
75
Table 4-27: Maximum High Side FET Time on Register
75
Table 4-28: Buck Cycle Count VREGO_A Register
75
Table 4-29: Buck Cycle Count VREGO_B Register
75
Table 4-30: Buck Cycle Count VREGO_C Register
76
Table 4-31: Buck Cycle Count VREGO_D Register
76
Table 4-32: Buck Cycle Count Alert VREGO_A Register
76
Table 4-33: Buck Cycle Count Alert VREGO_B Register
76
Table 4-34: Buck Cycle Count Alert VREGO_C Register
76
Table 4-35: Buck Cycle Count Alert VREGO_D Register
77
Table 4-36: Buck Regulator Output Ready Register
77
Table 4-37: Zero Cross Calibration VREGO_A Register
77
Power Sequencer and Always-On Domain Registers
78
Table 4-38: Zero Cross Calibration VREGO_B Register
78
Table 4-39: Zero Cross Calibration VREGO_C Register
78
Table 4-40: Zero Cross Calibration VREGO_D Register
78
Table 4-41: Power Sequencer and Always-On Domain Register Summary
78
Power Sequencer and Always-On Domain Register Details
79
Table 4-42: Low Power Control Register
79
Table 4-43: GPIO0 Low Power Wakeup Status Flags
80
Table 4-44: GPIO0 Low Power Wakeup Enable Registers
80
Table 4-45: GPIO1 Low Power Wakeup Status Flags
80
Table 4-46: GPIO1 Low Power Wakeup Enable Registers
80
Table 4-47: Peripheral Low Power Wakeup Status Flags
81
Table 4-48: Peripheral Low Power Wakeup Enable Register
82
Table 4-49: RAM Shutdown Control Register
83
Table 4-50: Low Power VDD Power down Register
84
Global Control Registers (GCR)
85
Table 4-51: BACKUP Return Vector Register
85
Table 4-52: BACKUP Aod Register
85
Table 4-53: Global Control Register Summary
85
Global Control Register Details (GCR)
86
Table 4-54: System Control Register
86
Table 4-55: Reset Register 0
87
Table 4-56: System Clock Control Register
90
Table 4-57: Power Management Register
92
Table 4-58: Peripheral Clock Divisor Register
93
Table 4-59: Peripheral Clock Disable Register 0
94
Table 4-60: Memory Clock Control Register
96
Table 4-61: Memory Zeroization Control Register
98
Table 4-62: System Status Flag Register
100
Table 4-63: Reset Register 1
100
Table 4-64: Peripheral Clock Disable Register 1
102
Table 4-65: Event Enable Register
105
Table 4-66: Revision Register
106
Table 4-67: System Status Interrupt Enable Register
106
Table 4-68: Error Correction Coding Error Register
106
Table 4-69: Error Correction Not Double Error Detected Register
107
Table 4-70: Error Correction Coding Interrupt Enable Register
109
Table 4-71: Error Correction Coding Address Register
110
Table 4-72: Bluetooth LDO Control Register
110
Table 4-73: Bluetooth LDO Delay Count Register
112
Table 4-74: General Purpose 0 Register
112
Table 4-75: Arm Peripheral Bus Asynchronous Bridge Select Register
112
Function Control Registers
113
Function Control Register Details
113
Table 4-76: Function Control Register Summary
113
Table 4-77: Function Control Register 0
113
AES Key Registers
114
AES Key Register Details
114
Table 4-78: AES Key Register Summary
114
Table 4-79: AES Key 0 and 1 Registers
114
Table 4-80: AES Key 2 and 3 Registers
114
5 Interrupts and Exceptions
115
Features
115
Interrupt Vector Table
115
Table 5-1: MAX32665-MAX32668 Interrupt Vector Table
115
6 General-Purpose I/O and Alternate Function Pins (GPIO)
119
Instances
119
Table 6-1: MAX32665-MAX32668 GPIO Pin Count
119
Table 6-2: MAX32665-MAX32668 GPIO and Alternate Function Matrix, 140 WLP
120
Table 6-3: MAX32665-MAX32668 GPIO Pin Configuration
121
Table 6-4: MAX32665-MAX32668 Input Mode Configuration
121
Table 6-5: MAX32665-MAX32668 Output Mode Configuration
122
Table 6-6: MAX32665-MAX32668 GPIO Port Interrupt Vector Mapping
122
Usage
123
Reset State
123
Input Mode Configuration
123
Output Mode Configuration
123
Alternate Function Configuration
123
Configuring GPIO (External) Interrupts
123
GPIO Interrupt Handling
124
Using GPIO for Wakeup from Low Power Modes
124
Table 6-7: MAX32665-MAX32668 GPIO Wakeup Interrupt Vector
124
Registers
125
Table 6-8: GPIO Register Summary
125
Register Details
126
Table 6-9: GPIO Port N Configuration Enable Bit 0 Register
126
Table 6-10: GPIO Port N Configuration Enable Atomic Set Bit 0 Register
126
Table 6-11: GPIO Port N Configuration Enable Atomic Set Bit 0 Register
126
Table 6-12: GPIO Port N Output Enable Register
126
Table 6-13: GPIO Port N Output Enable Atomic Set Register
127
Table 6-14: GPIO Port N Output Enable Atomic Clear Register
127
Table 6-15: GPIO Port N Output Register
127
Table 6-16: GPIO Port N Output Atomic Set Register
127
Table 6-17: GPIO Port N Output Atomic Clear Register
127
Table 6-18: GPIO Port N Input Register
128
Table 6-19: GPIO Port N Interrupt Mode Register
128
Table 6-20: GPIO Port N Interrupt Polarity Register
128
Table 6-21: GPIO Port N Input Enable Register
128
Table 6-22: GPIO Port N Interrupt Enable Register
129
Table 6-23: GPIO Port N Interrupt Enable Atomic Set Register
129
Table 6-24: GPIO Port N Interrupt Enable Atomic Clear Register
129
Table 6-25: GPIO Port N Interrupt Status Register
129
Table 6-26: GPIO Port N Interrupt Clear Register
129
Table 6-27: GPIO Port N Wakeup Enable Register
130
Table 6-28: GPIO Port N Wakeup Enable Atomic Set Register
130
Table 6-29: GPIO Port N Wakeup Enable Clear Register
130
Table 6-30: GPIO Port N Interrupt Dual Edge Mode Register
130
Table 6-31: GPIO Port N Pullup Pulldown Selection 0 Register
130
Table 6-32: GPIO Port N Pullup Pulldown Selection 1 Register
131
Table 6-33: GPIO Port N Configuration Enable Bit 1 Register
131
Table 6-34: GPIO Port N Configuration Enable Atomic Set, Bit 1 Register
131
Table 6-35: GPIO Port N Configuration Enable Atomic Clear, Bit 1 Register
131
Table 6-36: GPIO Port N Configuration Enable Bit 2 Register
132
Table 6-37: GPIO Port N Configuration Enable Atomic Set Bit 2 Register
132
Table 6-38: GPIO Port N Configuration Enable Atomic Clear Bit 2 Register
132
Table 6-39: GPIO Port N Output Drive Strength Bit 0 Register
132
Table 6-40: GPIO Port N Output Drive Strength Bit 0 Register
132
Table 6-41: Gpion Pulldown/Pullup Strength Select Register
133
Table 6-42: Gpion Supply Voltage Select Register
133
7 Flash Controller (FLC)
134
Instances
134
Usage
134
Table 7-1: MAX32665-MAX32668 Internal Flash Memory Organization
134
Clock Configuration
135
Flash Write Width
135
Lock Protection
135
Table 7-2: Valid Addresses Flash Writes
135
Flash Write
136
Page Erase
136
Mass Erase
137
Flash Error Correction Coding
137
Flash Controller Registers
137
Table 7-3: Flash Controller Registers
137
Flash Controller Register Details
138
Table 7-4: Flash Controller Address Pointer Register
138
Table 7-5: Flash Controller Clock Divisor Register
138
Table 7-6: Flash Controller Control Register
138
Table 7-7: Flash Controller Interrupt Register
139
Table 7-8: Flash Controller ECC Data Register
140
Table 7-9: Flash Controller Data Register 0
140
Table 7-10: Flash Controller Data Register 1
140
Table 7-11: Flash Controller Data Register 2
140
Table 7-12: Flash Controller Data Register 3
141
8 External Memory
142
Overview
142
SPI Execute-In-Place Flash (SPIXF)
142
SPIXF Master Controller
143
Figure 8-1. Simplified SPIXF Block Diagram
143
Figure 8-2. Simplified Block Diagram
144
Table 8-1: SPI Header Format
145
Table 8-2: Clock Polarity and Phase Combinations
147
Figure 8-3. SPIXFC Transaction Delay
149
Table 8-3: Encrypted Data Write Order to SPIX Flash Memory
150
Table 8-4. SPIXF Master Controller Register Offsets, Names, Access and Description
151
Table 8-5. SPIXF Controller Configuration Register
151
Table 8-6. SPIXF Controller Slave Select Polarity Register
152
Table 8-7. SPIXF Controller General Control Register
153
Table 8-8. SPIXF Controller FIFO Control and Status Register
154
Table 8-9. SPIXF Controller Special Control Register
155
Table 8-10. SPIXF Controller Interrupt Status Register
156
Table 8-11. SPIXF Controller Interrupt Enable Register
157
SPIXF Master
158
Table 8-12. SPIXF Master Controller FIFO Register Offsets, Names, Access and Description
158
Table 8-13. SPIXF Master Controller TX FIFO Register
158
Table 8-14. SPIXF Master Controller TX FIFO Register
158
Figure 8-4. Supported SPI Configuration
159
Figure 8-5. SPIXFM Delay Configuration
160
Table 8-15. SPIXFM Master Register Offsets, Names, Access and Description
162
Table 8-16. SPIXFM Configuration Register
162
Table 8-17. SPIXFM Fetch Control Register
163
Table 8-18. SPIXFM Mode Control Register
164
Table 8-19. SPIXFM Mode Data Register
165
Table 8-20. SPIXFM SCK Feedback Control Register
165
Table 8-21. SPIXFM I/O Control Register
165
Table 8-22. SPIXFM Memory Security Control Register
166
Table 8-23. SPIXFM Bus Idle Detection
166
SPI Execute-In-Place RAM (SPIXR)
167
SPIXR Master Controller Registers
168
Figure 8-6. Simplified SPIXR Block Diagram
168
Table 8-24. SPIXR Master Controller Register Offsets, Names, Access and Descriptions
168
SPIXR Register Details
169
Table 8-25. SPIXR FIFO Data Register
169
Table 8-26. SPIXR Master Signals Control Register
169
Table 8-27. SPIXR Transmit Packet Size Register
170
Table 8-28. SPIXR Static Configuration Register
170
Table 8-29. SPIXR Slave Select Timing Register
171
Table 8-30. SPIXR Master Baud Rate Generator
172
Table 8-31. SPIXR DMA Control Register
173
Table 8-32. SPIXR Interrupt Status Flag Register
174
Table 8-33. SPIXR Interrupt Enable Register
175
Table 8-34. SPIXR Wakeup Flag Register
176
Table 8-35. SPIXR Wakeup Enable Register
177
Table 8-36. SPIXR Active Status Register
177
Table 8-37. SPIXR External Memory Control Register
177
SPIXR Cache Controller (SRCC)
178
Features
178
Enabling the SRCC
178
Disabling the SRCC
178
SRCC Registers
179
SRCC Register Details
179
Table 8-38: External Memory Cache Controller Register Addresses and Descriptions
179
Table 8-39: SRCC Cache ID Register
179
Table 8-40: SRCC Memory Size Register
179
Table 8-41: SRCC Cache Control Register
179
Table 8-42: SRCC Invalidate Register
180
Secure Digital Host Controller
181
Instances
182
Figure 8-7: SDHC Block Diagram
182
Table 8-43: MAX32665-MAX32668 SDHC Alternate Function Mapping to SDHC Specification Pin Names
182
SDHC Peripheral Clock Selection
183
Usage
183
Figure 8-8: SD Bus Protocol - no Response and no Data Operations
183
SD Command Generation
184
Figure 8-9: SD Bus Protocol - Multi-Block Read Operation
184
Figure 8-10: SD Bus Protocol - Multi Block Write Operation
184
Table 8-44: Registers Used to Generate SD Commands
184
SDHC Registers
185
Table 8-45: SDHC Register Offsets, Names and Descriptions
185
SDHC Register Details
186
Table 8-46: SDHC SDMA System Address / Argument Register
186
Table 8-47: SDHC SDMA Block Size Register
187
Table 8-48: SDHC SDMA Block Count Register
188
Table 8-49: SDHC SDMA Argument 1 Register
188
Table 8-50: SDHC SDMA Transfer Mode Register
188
Table 8-51: Summary of How Register Settings Determine Type of Data Transfer
190
Table 8-52: SDHC Command Register
190
Table 8-53: Relationship between Parameters and the Name of Response Type
191
Table 8-54: SDHC Response 0 Register
191
Table 8-55: SDHC Response 1 Register
191
Table 8-56: SDHC Response 2 Register
191
Table 8-57: SDHC Response 3 Register
192
Table 8-58: SDHC Response 4 Register
192
Table 8-59: SDHC Response 5 Register
192
Table 8-60: SDHC Response 6 Register
192
Table 8-61: SDHC Response 7 Register
193
Table 8-62: SDHC Response Register Mapping to SD Host Controller Response Register Convention
193
Table 8-63: Kind of SD Card Response Mapping to SDHC Response Registers
193
Table 8-64: SDHC Buffer Data Port Register
193
Table 8-65: SDHC Present State Register
193
Table 8-66: SDHC Host Control 1 Register
196
Table 8-67: SDHC Power Control Register
197
Table 8-68: SDHC Block Gap Control Register
197
Table 8-69: SDHC Wakeup Control Register
199
Table 8-70: SDHC Clock Control Register
199
Table 8-71: SDHC Timeout Control Register
201
Table 8-72: SDHC Software Reset Register
202
Table 8-73: SDHC Normal Interrupt Status Register
203
Table 8-74: Transfer Complete and Data Timeout Error Priority and Status
205
Table 8-75: Command Complete and Command Timeout Error Priority and Status
205
Table 8-76: SDHC Error Interrupt Status Register
205
Table 8-77: SDHC Normal Interrupt Status Register
207
Table 8-78: SDHC Error Interrupt Status Enable Register
208
Table 8-79: SDHC Normal Interrupt Signal Enable Register
209
Table 8-80: SDHC Error Interrupt Signal Enable Register
210
Table 8-81: SDHC Auto CMD Error Status Register
211
Table 8-82: SDHC Host Control 2 Register
212
Table 8-83: SDHC Capabilities Register 0
213
Table 8-84: SDHC Capabilities Register 1
215
Table 8-85: SDHC Maximum Current Capabilities Register
216
Table 8-86: SDHC Force Event Register for Auto CMD Error Status Register
216
Table 8-87: SDHC Force Event Register for Error Interrupt Status
216
Table 8-88: SDHC ADMA Error Status Register
217
Table 8-89: SDHC ADMA System Address Register 0
218
Table 8-90: SDHC ADMA System Address Register 1
219
Table 8-91: Preset Value Register Example
219
Table 8-92: Preset Value Register Selection Conditions
219
Table 8-93: SDHC Preset Value 0 to Preset Value 7 Registers
220
Table 8-94: SDHC Slot Interrupt Status Register
220
Table 8-95: SDHC Host Controller Version Register
221
9 Standard DMA (DMAC)
222
Instances
222
DMA Channel Operation (DMACH)
223
DMA Channel Arbitration and DMA Bursts
223
Table 9-1: MAX32665-MAX32668 DMAC and Channel Instances
223
DMA Source and Destination Addressing
224
Table 9-2: MAX32665-MAX32668 DMAC Source and Destination by Peripheral
224
Data Movement from Source to DMA
226
Data Movement from the DMA to Destination
226
Table 9-3: Data Movement from Source to DMA FIFO
226
Table 9-4: Data Movement from the DMA FIFO to Destination
226
Usage
227
Count-To-Zero (CTZ) Condition
227
Chaining Buffers
228
Figure 9-1: DMA Block-Chaining Flowchart
229
DMA Interrupts
230
Channel Timeout Detect
230
Table 9-5: DMA Channel Timeout Configuration
230
Memory-To-Memory DMA
231
DMAC Registers
231
DMAC Register Details
231
Table 9-6: DMAC Register Summary
231
Table 9-7: Dmacn Control Register
231
DMA Channel Registers
232
DMAC Channel Registers
232
Table 9-8: Dmacn Interrupt Register
232
Table 9-9: Standard DMA Channel 0 to Channel 7 Register Summary
232
Table 9-10: DMACH Channel Registers Summary
232
DMA Channel Register Details
233
Table 9-11: Dmachn Configuration Register
233
Table 9-12: DMA Status Register
234
Table 9-13: Dmachn Source Register
235
Table 9-14: DMA Channel N Destination Register
236
Table 9-15: DMA Channel N Count Register
236
Table 9-16: DMA Channel N Source Reload Register
236
Table 9-17: DMA Channel N Destination Reload Register
236
Table 9-18: DMA Channel N Count Reload Register
237
10 Cyclic Redundancy Check Engine (CRC)
238
Instances
239
Linear Feedback Shift Register (LFSR)
239
Table 10-1: Common CRC Polynomials
239
Registers
240
Figure 10-1: Galois Field CRC and LFSR Architecture
240
Table 10-2: CRC Register Summary
240
Register Details
241
Table 10-3: CRC Control Register
243
Table 10-4: CRC DMA Source Register
243
Table 10-5: CRC DMA Destination Register
243
Table 10-6: CRC DMA Count Register
243
Table 10-7: CRC Data Input Registers
244
Table 10-8: CRC Data Output Registers
244
Table 10-9: CRC Polynomial Register
244
Table 10-10: CRC Value Register
245
Table 10-11: CRC Pseudo-Random Number Generator Register
245
11 Analog to Digital Converter and Comparators (ADC)
246
Features
246
Instances
246
Table 11-1: MAX32665-MAX32668 ADC Peripheral Pins
246
Architecture
247
Figure 11-1: Analog to Digital Converter Block Diagram
248
Clock Configuration
249
Table 11-2: ADC Clock Frequency and ADC Conversion Time (�������������� = 96������, ����
249
Power-Up Sequence
250
Conversion
250
Reference Scaling and Input Scaling
250
AIN0 - AIN7 Scale Limitations
251
Scale Limitations for All Other Input Channels
251
Data Conversion Output Alignment
251
Table 11-3: Input and Reference Scale Support by ADC Input Channel
251
Data Conversion Value Equations
252
Table 11-4: ADC Data Register Alignment Options
252
Data Limits and out of Range Interrupts
253
Figure 11-2: ADC Limit Engine
253
Power-Down Sequence
254
Comparator Operation
254
Registers
255
Register Details
255
Table 11-5. ADC Registers Summary
255
Table 11-6: ADC Control Register
255
Table 11-7: ADC Status Register
257
Table 11-8: ADC Data Register
257
Table 11-9: ADC Interrupt Control Register
257
Table 11-10: ADC Limit 0 to 3 Registers
258
12 Uart
260
Instances
260
UART Frame
260
Figure 12-1: UART Frame Diagram
260
UART Interrupts
261
UART Baud Rate Clock Source
261
UART Baud Rate Calculation
261
Table 12-1: UART Interrupt Conditions
261
Table 12-2: Example Baud Rate Calculation Results, Target Bit Rate = 1.8Mbps
262
UART Configuration and Operation
263
Wakeup Time
263
Hardware Flow Control
263
Registers
263
Register Details
264
Table 12-3: UART Register Summary
264
Table 12-4: UART Control 0 Register
264
Table 12-5: UART Control 1 Register
266
Table 12-6: UART Status Register
266
Table 12-7: UART Interrupt Enable Register
267
Table 12-8: UART Interrupt Flags Register
268
Table 12-9: UART Rate Integer Register
270
Table 12-10: UART Baud Rate Decimal Register
270
Table 12-11: UART FIFO Register
270
Table 12-12: UART DMA Configuration Register
270
Table 12-13: UART Transmit FIFO Data Output Register
271
1 I C Master/Slave Serial Communications Peripheral (I2C)
272
Figure 13-1: I C Block Diagram
273
C Master/Slave Features
274
Instances
274
Table 13-1: MAX32665 - MAX32668 I
274
I 2 C Overview
275
I 2 C Bus Terminology
275
I 2 C Transfer Protocol Operation
275
START and STOP Conditions
275
Master Operation
275
Acknowledge and Not Acknowledge
275
Table 13-2: I 2 C Bus Terminology
275
Bit Transfer Process
276
Figure 13-2: I C Write Data Transfer
276
I 2 C Configuration and Usage
277
SCL and SDA Bus Drivers
277
SCL Clock Configurations
277
SCL Clock Generation for Standard, Fast and Fast-Plus Modes
277
SCL Clock Generation for Hs-Mode
278
Figure 13-3: I C SCL Timing for Standard, Fast, and Fast-Plus Modes
278
I 2 C Addressing
279
Table 13-3: Calculated I
279
Table 13-4: I 2 C Slave Address Format
279
I 2 C Master Mode Operation
280
I 2 C Slave Mode Operation
283
I 2 C Interrupt Sources
288
TX FIFO and RX FIFO
288
TX FIFO Preloading
289
Interactive Receive Mode (IRXM)
290
Clock Stretching
291
I 2 C Bus Timeout
291
I 2 C DMA Control
292
Registers
292
Table 13-5: I 2 C Registers
292
Register Details
293
Table 13-6: I 2 C Control 0 Register
293
Table 13-7: I C Status Register
294
Table 13-8: I C Interrupt Flag 0 Register
295
Table 13-9: I C Interrupt Enable 0 Register
297
Table 13-10: I C Interrupt Flag 1 Register
299
Table 13-11: I C Interrupt Enable 1 Register
299
Table 13-12: I C FIFO Length Register
299
Table 13-13: I C Receive Control 0 Register
299
Table 13-14: I C Receive Control 1 Register
300
Table 13-15: I C Transmit Control 0 Register
301
Table 13-16: I C Transmit Control 1 Register
302
Table 13-17: I C Data Register
302
Table 13-18: I C Master Mode Control Register
303
Table 13-19: I C SCL Low Control Register
303
Table 13-20: I C SCL High Control Register
303
Table 13-21: I C Hs-Mode Clock Control Register
304
Table 13-22: I C Timeout Register
304
Table 13-23: I C DMA Register
304
Table 13-24: I C Slave Address Register
305
14 Quad Serial Peripheral Interface (SPI)
306
Figure 14-1: QSPI Block Diagram
306
Instances
307
Table 14-1: MAX32665-MAX32668 SPI Instances
307
SPI Formats
308
Four-Wire SPI
308
Table 14-2: MAX32665-MAX32668 QSPI Signal Mapping
308
Table 14-3: Four-Wire Format Signals
308
Three-Wire SPI
309
Figure 14-2: 4-Wire SPI Connection Diagram
309
Table 14-4: Three-Wire Format Signals
309
Pin Configuration
310
Qspin Alternate Function Mapping
310
Four-Wire Format Configuration
310
Three-Wire Format Configuration
310
Figure 14-3: Generic 3-Wire SPI Master to Slave Connection
310
Dual Mode Format Configuration
311
Quad Mode Format Pin Configuration
311
QSPI Clock Configuration
311
Serial Clock
311
Figure 14-4: Dual Mode SPI Connection Diagram
311
SPI Peripheral Clock
312
Master Mode Serial Clock Generation
312
Clock Phase and Polarity Control
312
Figure 14-5: SCK Clock Rate Control
312
Qspin Fifos
313
QSPI Interrupts and Wakeups
313
Figure 14-6: SPI Clock Polarity
313
Table 14-5. SPI Modes Clock Phase and Polarity Operation
313
Registers
314
Table 14-6: Qspin Base Address Offsets, Register Names, Access and Descriptions
314
Register Details
315
Table 14-7: Qspin FIFO Data Register
315
Table 14-8: Qspin Control 0 Register
315
Table 14-9: Qspin Transmit Packet Size Register
316
Table 14-10: Qspin Control 2 Register
316
Table 14-11: Qspin Slave Select Timing Register
318
Table 14-12: Qspin Master Clock Configuration Registers
319
Table 14-13: Qspin DMA Control Registers
319
Table 14-14: Qspin Interrupt Status Flags Registers
320
Table 14-15: Qspin Interrupt Enable Registers
321
Table 14-16: Qspin Wakeup Status Flags Registers
322
Table 14-17: Qspin Wakeup Enable Registers
323
Table 14-18: Qspin Slave Select Timing Registers
323
15 Htimer (HT)
324
Overview
324
Alarm Functions
324
Long-Interval Alarm
324
Short-Interval Alarm
324
Register Access Control
325
Register Write Protection
325
Register Read Protection
325
Count Register Access
325
Alarm Register Access
325
Registers
326
Register Details
326
Table 15-1. Htimer Registers Summary
326
Table 15-2: Htimer Long-Interval Counter Register
326
Table 15-3: Htimer Short-Interval Counter Register
326
Table 15-4: Htimer Long-Interval Alarm Register
326
Table 15-5: Htimer Short-Interval Alarm Register
326
Table 15-6: Htimer Control Register
327
16 Timers
329
Features
329
Basic Operation
329
Timer Pin Functionality
330
One-Shot Mode (000B)
330
Figure 16-1: One-Shot Mode Diagram
330
One-Shot Mode Configuration
331
One-Shot Mode Timer Period
331
Continuous Mode (001B)
331
Continuous Mode Timer Period
332
Figure 16-2: Continuous Mode Diagram
332
Continuous Mode Configuration
333
Counter Mode (010B)
334
Figure 16-3: Counter Mode Diagram
334
Counter Mode Configuration
335
Counter Mode Timer Period
335
PWM Mode (011B)
336
PWM Mode Timer Period
336
PWM Mode Configuration
336
Capture Mode (100B)
338
Figure 16-4: Capture Mode Diagram
338
Capture Mode Configuration
339
Capture Mode Timer Period
339
Compare Mode (101B)
339
Compare Mode Timer Period
340
Figure 16-5: Counter Mode Diagram
340
Compare Mode Configuration
341
Gated Mode (110B)
342
Figure 16-6: Gated Mode Diagram
342
Gated Mode Configuration
343
Gated Mode Timer Period
343
Capture/Compare Mode (111B)
344
Capture/Compare Timer Period
344
Capture/Compare Configuration
344
Timer Registers
345
Table 16-1: Timer Register Offset, Names, Access and Descriptions
345
Table 16-2: Timer Count Registers
345
Table 16-3: Timer Compare Registers
345
Table 16-4: Timer Interrupt Registers
346
Table 16-5: Timer Control Registers
346
Table 16-6: Timer Non-Overlapping Compare Registers
348
17 Pulse Train Engine (PT)
349
Instances
349
Pulse Train Engine Features
349
Engine
349
Pulse Train Output Modes
350
Enabling and Disabling a Pulse Train Output
351
Atomic Pulse Train Output Enable and Disable
351
Pulse Train Atomic Enable
351
Pulse Train Atomic Disable
352
Pulse Train Halt and Disable
352
Pulse Train Interrupts
352
Registers
352
Table 17-1: Pulse Train Engine Register Summary
352
Register Details
354
Table 17-2: Pulse Train Engine Global Enable/Disable Register
354
Table 17-3: Pulse Train Engine Resync Register
356
Table 17-4:Pulse Train Engine Stopped Interrupt Flag Register
359
Table 17-5: Pulse Train Engine Interrupt Enable Register
361
Pulse Train Engine Safe Enable Register
363
Table 17-6: Pulse Train Engine Safe Enable Register
363
Pulse Train Engine Safe Disable Register
364
Table 17-7: Pulse Train Engine Safe Disable Register
364
Table 17-8: Pulse Train Engine Configuration Register
366
Table 17-9: Pulse Train Mode Bit Pattern Register
366
Table 17-10: Pulse Train N Loop Configuration Register
367
Table 17-11: Pulse Train N Automatic Restart Configuration Register
367
18 Real-Time Clock (RTC)
369
Overview
369
Figure 18-1. MAX32665-MAX32668 RTC Block Diagram (12-Bit Sub-Second Counter)
369
Instances
370
Register Access Control
370
RTC_SEC and RTC_SSEC Read Access Control
370
Table 18-1. MAX32665-MAX32668 RTC Counter and Alarm Registers
370
Table 18-2. RTC Register Access
370
RTC Write Access Control
371
RTC Alarm Functions
371
Time-Of-Day Alarm
371
Figure 18-2. RTC Busy/Ready Signal Timing
371
Sub-Second Alarm
372
RTC Interrupt and Wakeup Configuration
373
Square Wave Output
373
Figure 18-3. RTC Interrupt/Wakeup Diagram Wakeup Function
373
RTC Calibration
374
Table 18-3. MAX32665-MAX32668 RTC Square Wave Output Configuration
374
Figure 18-4. Internal Implementation of Digital Trim, 4Khz
375
Registers
376
Register Details
376
Table 18-4. RTC Register Summary
376
Table 18-5. RTC Seconds Counter Register
376
Table 18-6. RTC Sub-Second Counter Register (12-Bit)
376
Table 18-7. RTC Time-Of-Day Alarm Register
377
Table 18-8. RTC Sub-Second Alarm Register
377
Table 18-9. RTC Control Register
377
Table 18-10. RTC 32Khz Oscillator Digital Trim Register
379
Table 18-11. RTC 32Khz Oscillator Control Register
379
19 Watchdog Timer (WDT)
380
Features
381
Usage
381
Figure 19-1: Watchdog Timer Block Diagram
381
Interrupt and Reset Period Timeout Configuration
382
Timed Access Protection
382
Table 19-1: Watchdog Timer Interrupt Period Fsys_Clk = 96Mhz and Fpclk = 48Mhz
382
Enabling the Watchdog Timer
383
Enable Sequence
383
Disabling the Watchdog Timer
383
Manual Disable
383
Automatic Disable
383
Resetting the Watchdog Timer
383
Reset Sequence
383
Detection of a Watchdog Reset Event
383
Registers
383
Table 19-2: Watchdog Timer Register Offsets, Names and Descriptions
383
Register Details
384
Table 19-3: Watchdog Timer Control Register
384
Table 19-4: Watchdog Timer Reset Register
386
20 Wire Master (OWM)
387
Instances
387
Pins and Configuration
388
Pin Configuration
388
1-Wire I/O (OWM_IO)
388
Pullup Enable (OWM_PE)
388
Clock Configuration
388
Table 20-1: OWM Pin to Alternate Function Mapping
388
1-Wire Protocol
389
Networking Layers
389
Figure 20-1: 1-Wire Signal Interface
389
Figure 20-2: 1-Wire Reset Pulse
390
Figure 20-3: 1-Wire Write Time Slot
391
Figure 20-4: 1-Wire Read Time Slot
391
Figure 20-5: 1-Wire ROM ID Fields
392
Table 20-2: 1-Wire ROM Commands
392
Read ROM Command
393
Skip ROM and Overdrive Skip ROM Commands
393
Table 20-3: 1-Wire Slave Device ROM ID Field
393
Match ROM and Overdrive Match ROM Commands
394
Search ROM Command
394
Search ROM Accelerator Operation
394
Resume Communication Command
395
1-Wire Operation
396
Resetting the OWM
396
1-Wire Data Reads
396
Reading a Single Bit Value from the 1-Wire Bus
396
Reading an 8-Bit Value from the 1-Wire Bus
397
Registers
397
Table 20-4: OWM Register Summary
397
Register Details
398
Table 20-5: OWM Configuration Register
398
Table 20-6: OWM Clock Divisor Register
399
Table 20-7: OWM Control/Status Register
399
Table 20-8: OWM Data Register
400
Table 20-9: OWM Interrupt Flag Register
400
Table 20-10: OWM Interrupt Enable Register
401
21 USB 2.0 High-Speed (USBHS) Host Interface with PHY
402
Instances
402
USBHS Bus Signals
403
USBHS Device Endpoints
403
Table 21-1: USB Bus States Indicated by the Differential Pair (D+, D-)
403
USBHS Reset and Clock
404
USBHS SUSPEND Mode and RESUME States
404
Packet Size
405
Endpoint 0 Control Transactions
405
Endpoint 0 Error Handling
405
Bulk Endpoints Operation and Options
405
Bulk in Endpoints
405
Table 21-2: USB Bulk in Endpoints Options
405
Bulk out Endpoints
406
Interrupt Endpoints
407
Interrupt in Endpoints
407
Interrupt out Endpoints
407
Isochronous Endpoints
407
Isochronous in Endpoints
407
Table 21-3: USB Isochronous in Endpoint Options
407
Isochronous out Endpoints
408
Table 21-4: USB Isochronous out Endpoint Options
408
USBHS Device Registers
409
Table 21-5: USBHS Device Register Offsets, Names, Access, and Descriptions
409
USBHS Device Register Details
410
Table 21-6: USBHS Device Address Register
410
Table 21-7: USBHS Power Management Register
410
Table 21-8: USBHS in Endpoint Interrupt Flags Register
411
Table 21-10: USBHS in Endpoint Interrupt Enable Register
412
Table 21-9: USBHS out Endpoint Interrupt Flags Register
412
Table 21-11: USBHS out Endpoint Interrupt Enable Register
414
Table 21-12: USBHS Signaling Interrupt Status Flag Register
415
Table 21-13: USBHS Signaling Interrupt Enable Register
415
Table 21-14: USBHS Frame Number Register
415
Endpoint Register Access Control
416
Table 21-15: USBHS Register Index Select Register
416
Table 21-16: USBHS Test Mode Register
416
Table 21-17: USB Memory Mapped Register Access for Endpoints 1 to 11
416
Table 21-18: USBHS in Endpoint Maximum Packet Size Register
417
Table 21-19: USBHS in Endpoint Lower Control and Status Register
417
USBHS in Endpoint Lower Control and Status Registers
417
USBHS in Endpoint Maximum Packet Size Registers
417
Table 21-20: USBHS Endpoint 0 Control Status Register
418
USBHS Endpoint 0 Control Status Register
418
Table 21-21: USBHS in Endpoint Upper Control Register
419
USBHS in Endpoint Upper Control Registers
419
Table 21-22: USBHS out Endpoint Maximum Packet Size Register
420
Table 21-23: USBHS out Endpoint Lower Control Status Register
421
Table 21-24: USBHS out Endpoint Upper Control Status Register
422
Table 21-25: USBHS Endpoint out FIFO Byte Count Register
423
Table 21-26: USBHS Endpoint 0 in FIFO Byte Count Register
423
Table 21-27: USBHS FIFO for Endpoint N Register
423
Table 21-28: USBHS Endpoint Count Info Register
424
Table 21-29: USBHS RAM Info Register
424
Table 21-30: USBHS Soft Reset Control Register
424
Table 21-31: USBHS Early DMA Register
424
Table 21-32: USBHS Hi-Speed Chirp Timeout Register
425
Table 21-33: USBHS Hi-Speed RESUME Delay Register
425
22 Bluetooth 5 Low Energy (LE) Radio
426
Power-Efficient Design
426
Bluetooth Hardware Accelerator
426
Arm Cordio®-B50 Software Stack
426
Figure 22-1: MAX32665-MAX32668 Bluetooth Stack Overview
427
Pins
428
Configuration
428
Documentation
428
23 Trust Protection Unit (TPU)
429
Dedicated Cryptographic DMA Engine (CDMA)
430
Figure 23-1. Cryptographic Accelerator Block Diagram
430
Fifos
431
Figure 23-2. DMA Block Diagram
431
Table 23-1. Cryptographic Accelerator DMA Sources
431
Cache Security
432
Direct FIFO Access
432
Block Cipher Accelerator
432
Figure 23-3. Block Cipher Block Diagram
433
Table 23-2. Symmetric Block Ciphers
433
Cipher Key Storage and Initialization
434
Operation
435
Hash Function Accelerator
435
Last Message Block Padding
436
Figure 23-4. Block Cipher Diagram
436
Table 23-3. Hash Functions
436
CRC Engine (Galois Field Accelerator)
437
Hamming Code Accelerator
437
Figure 23-5. Hamming XOR Calculations
438
Modular Arithmetic Accelerator
439
Operation
440
MAA Memory
440
Table 23-4. Cryptographic Memory Segments
440
Table 23-5. MAA Memory Segments and Locations
441
Table 23-6. MAA Memory Blinding Example (Memory Instance 0, MAWS > 1024)
441
True Random Number Generation
442
Registers
442
Write Access
443
Read Access
443
Table 23-7. Cryptographic Registers, Offsets and Descriptions
443
Register Details
444
Table 23-8: Cryptographic Control Register
444
Table 23-9: Cipher Control Register
446
Table 23-10: Hash Control Register
447
Table 23-11: CRC Control Register
448
Table 23-12: Cryptographic DMA Source Register
449
Table 23-13: Cryptographic DMA Destination Register
449
Table 23-14: Cryptographic DMA Count Register
449
Table 23-15: MAA Control Register
449
Table 23-16: Cryptographic Data Input Register
452
Table 23-17: Cryptographic Data Output Register
452
Table 23-18: CRC Polynomial Register
453
Table 23-19: CRC Value Register
453
Table 23-20: CRC PRNG Register
453
Table 23-21: Hamming Error Correction Code Register
453
Table 23-22: Cipher Initial Vector Register [3:0]
453
Table 23-23: Cipher Key Register [7:0]
454
Table 23-24: HASH Message Digest Register [15:0]
454
Table 23-25: Hash Message Size Registers
454
Table 23-26: MAA Word Size Register
455
Table 23-27: TRNG Control Register (Base Address 0X400B_5000)
456
Table 23-28: TRNG Data Register (Base Address 0X400B_5000)
456
24 Revision History
457
4
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Maxim Integrated MAX32665 Specifications
General
Brand
Maxim Integrated
Model
MAX32665
Category
Motherboard
Language
English
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