Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 166 of 457
SPIXFM I/O Control Register
SPIXFM_IO_CTRL
[0x001C]
Bits
Name
Access
Reset
Description
1
ss_ds
R/W
1
Slave Select Drive Strength
This bit controls the drive strength on the dedicated slave select pin.
0: Low Drive Strength.
1: Hi Drive Strength.
0
sck_ds
R/W
1
SCK Drive Strength
This bit controls the drive strength on the SCK pin.
0: Low Drive Strength.
1: Hi Drive Strength.
Table 8-22. SPIXFM Memory Security Control Register
SPIXFM Memory Security Control Register
SPIXFM_SEC_CTRL
[0x0020]
Bits
Name
Access
Reset
Description
31:2
-
R/W
0
Reserved for Future Use
Do not modify this field.
1
auth_disable
R/W
0
Integrity Enable.
0: Integrity checking enabled.
1: Integrity checking disabled.
0
dec_en
R/W
0
Decryption Enable.
0: Disable decryption of SPIXF data.
1: Enable decryption of SPIXF data.
Table 8-23. SPIXFM Bus Idle Detection
SPIXFM Bus Idle Detection
SPIXFM_BUS_IDLE
[0x0024]
Bits
Name
Access
Reset
Description
31:16
-
R/W
0
Reserved for Future Use
Do not modify this field.
15:0
busidle
R/W
0
Bus Idle Timer Limit
A 16-bit timer will be triggered for each external access. The timer will be
restarted if another access is performed before the timer expires. When the
timer expires, slave select will be deactivated.
This register contains the limit (expiration) value for the timer. A value of 0 will
disable the bus idle detection and non-zero values enable bus idle detection.
This feature is useful when fetching code out of I-cache, ROM or in SLEEP and
DEEPSLEEP modes. When this number is too small, Slave Select will be
deactivated on every access, which may reduce current consumption, but
decreases performance.

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English