MAX32665-MAX32668 User Guide
Maxim Integrated Page 131 of 457
Table 6-32: GPIO Port n Pullup Pulldown Selection 1 Register
GPIO Port Pullup Pulldown Selection 1
GPIO Pullup Pulldown Selection 1
Input mode configuration for the associated GPIO pin. Input mode selection and
the selection of a weak or strong pullup or weak or strong pulldown resistor are
described in Table 6-4..
Table 6-33: GPIO Port n Configuration Enable Bit 1 Register
GPIO Port n Configuration Enable Bit 0
GPIO Configuration Enable, Bit 1
This bit, in conjunction with bits in Table 6-3: MAX32665—MAX32668 GPIO Pin
Configuration, configures the corresponding device pin as a GPIO or an
alternate function mode.
Some GPIO are not implemented all devices. The bits associated with
unimplemented GPIO should not be changed from their default value. See
Table 6-1: MAX32665—MAX32668 GPIO Pin Count concerning which pins are
available.
This bit’s setting does not affect input and interrupt functionality of the
associated pin.
Table 6-34: GPIO Port n Configuration Enable Atomic Set, Bit 1 Register
GPIO Port n Configuration Enable Atomic Set, Bit 1
GPIO Configuration Enable Atomic Set, Bit 1
Writing 1 to one or more bits sets the corresponding bits in the GPIOn_EN1
register.
0: No effect.
1: Corresponding bits in GPIOn_EN1 register set to 1.
Table 6-35: GPIO Port n Configuration Enable Atomic Clear, Bit 1 Register
GPIO Port n Configuration Enable Atomic Clear, Bit 1
GPIO Configuration Enable Atomic Clear, Bit 1
Writing 1 to one or more bits clears the corresponding bits in the
GPIOn_EN1 register.
0: No effect.
1: Corresponding bits in GPIOn_EN1 register cleared to 0.
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