MAX32665-MAX32668 User Guide
Maxim Integrated Page 350 of 457
17.3.1 Pulse Train Output Modes
Each pulse train output supports the following modes:
• Pulse Train Mode
• Bit Patter Length
• Square Wave Mode
17.3.1.1 Pulse Train Mode
When pulse train x (PTn) is configured in pulse train mode, the configuration also includes the bit length (up to 32-bits) of
the custom pulse train. This is configured using the 5-bit field PTn_RATE_LENGTH.mode.
PTn_RATE_LENGTH.mode = 1 (PTn configured in Square Wave mode)
PTn_RATE_LENGTH.mode > 1 (PTn configured in pulse train mode. The value of mode is the pattern bit length.)
PTn_RATE_LENGTH.mode =0 (PTn bit length configured for pulse train mode, 32-bit pattern)
If in pulse train Mode, Set the Bit Pattern
If an output is set to pulse train mode, then configure a custom bit pattern from 2-bits to 32-bits in length in the 32-bit
register PTn_TRAIN. The pattern is shifted out least significant bit (LSB) first. If the output is configured in Square Wave
mode, then the PTn_TRAIN register is ignored.
Equation 17-1: Pulse Train Mode Output Function
PTnTRAIN
BitpatternforPTn
Synchronize Two or More Outputs, if Needed
The write-only register PTG_RESYNC “PT Global Resync” allows two or more outputs to be reset and synchronized. Write to
any bit in PTG_RESYNC to simultaneously reset any outputs in pulse train mode to the beginning of the pattern (the LSB) set
in the PTn_TRAIN bit-pattern register, and reset the output to 0 for outputs in Square Wave mode.
17.3.1.2 Pulse Train Loop Mode
By default, a pulse train engine runs indefinitely until it is disabled by firmware.
A pulse train engine can be configured to repeat its pattern a specified number of times, called Loop mode. To select Loop
mode, write a non-zero value to the 16-bit field PTn_LOOP.count. When the pulse train engine is enabled, this field
decrements by 1 each time a complete pattern is shifted through the output pin. When the count reaches 0, the output is
halted, and the corresponding flag in the PTG_INTFL register is set.
17.3.1.3 Pulse Train Loop Delay
If the pulse train is configured in Loop mode, a delay can be inserted after each repeated output pattern. To enable a delay,
write the 12-bit field PTn_LOOP.delay with the number of Peripheral Clock cycles to delay between the most significant bit
(MSB) of the last pattern to the least-significant bit (LSB) of the next pattern. During this delay, the output is held at the
MSB of the last pattern. If the loop counter has not reached 0, then it is decremented when the next pattern starts.
17.3.1.4 Pulse Train Automatic Restart Mode
When an engine in pulse train mode is in Loop mode and stops when the loop count reaches 0, this is called a Stop Event. A
Stop Event can optionally trigger one or more pulse trains to restart from the beginning. This is called Automatic Restart
mode. While only pulse train engines operating in pulse train mode can operate in Loop mode and can optionally restart a
pulse train engine, Automatic Restart mode can trigger pulse train engines operating in pulse train mode or in Square Wave
mode.
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