MAX32665-MAX32668 User Guide
Maxim Integrated Page 154 of 457
SPIXF Controller General Control Register
SCK Drive and State
This bit reflects the state of the SCK. When in Bit-Bang mode
(SPIXFC_GEN_CTRL.bbmode = 1), this bit is written to control the output state of
the SCK.
0: SCK is 0.
1: SCK is 1.
Reserved for Future Use
Do not modify this field.
Slave Select Drive and State
This bit reflects the state of the slave select. This accounts for the polarity as
defined in the SPIXFC_SS_POL register. When in Bit-Bang mode, this bit is
written to control the output state of the slave select.
0: Selected Slave Select Output is 0
1: Selected Slave Select Output is 1.
Bit-Bang Mode
0: Disable Bit-Bang mode
1: Enable Bit-Bang mode
Receive FIFO Enable
Setting this bit enables the Receive FIFO. Clearing this bit disables the Receive
FIFO and places it into a reset state.
0: Disable result FIFO.
1: Enable result FIFO.
Transmit FIFO Enable
Setting this bit to 1 enables the Transmit FIFO. Clearing this bit disables the
Transmit FIFO and places it into reset state.
0: Disable Transmit FIFO.
1: Enable Transmit FIFO.
SPI Master enable
Setting this bit to 1 enables SPI Master for processing transactions. Clearing this
bit disables the SPI Master and puts the block into reset state.
0: Disable SPI Master, putting it into a reset state.
1: Enable SPI Master for processing transactions.
Table 8-8. SPIXF Controller FIFO Control and Status Register
SPIXF Controller FIFO Control and Status Register
Reserved for Future Use
Do not modify this field.
Receive FIFO Entry Count
Current number of used entries (bytes) in Receive FIFO. Writes to this field are
ignored.
Reserved for Future Use
Do not modify this field.