MAX32665-MAX32668 User Guide
Maxim Integrated Page 228 of 457
At this point, there are two possible responses depending on the value of the DMACHn_CFG.rlden:
1. If DMACHn_CFG.rlden = 1, then the DMACHn_SRC, DMACHn_DST, and DMACHn_CNT registers are loaded from the
reload registers, and the channel remains active and continues operating using the newly-loaded address/count
values and the previously programmed configuration values.
2. If DMACHn_CFG.rlden = 0, then the channel is disabled, and DMACHn_ST.ch_st is cleared.
9.5 Chaining Buffers
Chaining buffers reduces the DMA ISR response time and allows DMA to service requests without intermediate processing
from the CPU. Figure 9-1: DMA Block-Chaining Flowchart shows the procedure for generating a DMA transfer using one or
more chain buffers.
Configure the following reload registers to configure a channel for chaining:
• DMACHn_CFG
• DMACHn_SRC
• DMACHn_DST
• DMACHn_CNT
• DMAn_SRC_RLD
• DMAn_DST_RLD
• DMAn_CNT_RLD
Writing to any register while a channel is disabled is supported, but there are certain restrictions when a channel is enabled.
The DMACHn_ST.ch_st bit indicates whether the channel is enabled or not. Because an active channel might be in the
middle of an AHB read/write burst, do not write to the DMACHn_SRC, DMACHn_DST, or DMACHn_CNT registers while a
channel is active (DMACHn_ST.ch_st = 1). To disable any DMA channel, clear the DMACn_CN.chien bit. Then, poll the
DMACHn_ST.ch_st bit to verify that the channel is disabled.
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