MAX32665-MAX32668 User Guide
Maxim Integrated Page 263 of 457
target bit rate because it is the smallest value that results in DIV ≥ 1. Using 3 for UARTn_BAUD0.clkdiv,
UARTn_BAUD0.ibaud is 1, which is the integer portion of the 1.63 DIV calculation. The UARTn_BAUD1.dbaud field
calculation based on UARTn_BAUD0.clkdiv = 3, UARTn_BAUD0.ibaud = 1 and DIV = 1.63 is:
The resulting field settings for the example 1,843,200 bps rate are:
• UARTn_BAUD0.clkdiv = 3
• UARTn_BAUD0.ibaud = 1
• UARTn_BAUD1.dbaud = 77
12.6 UART Configuration and Operation
To configure the UART, perform the following steps:
1. Set UARTn_CTRL0 and UARTn_CTRL1 registers for desired parity, character size, stop bits, flow control, and
polarity.
2. Configure the desired baud rate by setting UARTn_BAUD0.clkdiv , UARTn_BAUD0.ibaud , and
UARTn_BAUD1.dbaud and described in UART Baud Rate Calculation.
3. Flush the Rx and Tx FIFO by setting UARTn_CTRL0.rxflush and UARTn_CTRL0.txflush
4. Clear any interrupts by writing 1 to UARTn_INT_FL.[9:0].
5. Enable interrupts as desired by setting individual fields in UARTn_INT_EN.
6. Enable the UART by setting UARTn_CTRL0.enable = 1.
12.7 Wakeup Time
Wakeup is configured by setting the UART I/O pins to GPIO with interrupt capability. Once a ATRAT bit is received, it
generates a GPIO interrupt. The firmware interrupt handler must re-configure the GPIO pins to UART functionality to
receive the first bit of the receive character. The time for the operation to configure GPIO pins and return for interrupt
service to do so is highly dependent upon the value of f
SYS_CLK
.
12.8 Hardware Flow Control
When hardware flow control is enabled, the CTS (Clear-to-send) and RTS (Request-to-Send) external signals are directly
managed by hardware without CPU intervention. RTS and CTS are active when flow control is enabled by setting the
register bit UARTn_CTRL0.flowctl = 1. The polarity of the CTS/RTS signals are configured with register bit
UARTn_CTRL0.flowpol and can be active low or active high.
In operation, the UART that wants to transmit data waits for its CTS input pin to be asserted. If CTS is asserted, then the
UART begins transmitting data to the slave UART. If during the transmission the UART notices CTS is deasserted, the UART
finishes transmitting the current character and then pauses to wait for CTS to return to an asserted level before
transmitting more data.
If this UART is receiving data, and the Receive FIFO reaches the level set in UARTn_CTRL1.rts_fifo_lvl, then the RTS signal of
this UART is deasserted, informing the transmitting UART to stop sending data to this UART to prevent data overflow.
Transmission resumes when the level of the Receive FIFO drops below UARTn_CTRL1.rts_fifo_lvl, which automatically
asserts RTS.
12.9 Registers
See Table 3-1: APB Peripheral Base Address Map for this peripheral/module's base address. If multiple instances are
provided, each will have a unique base address. Unless specified otherwise, all fields are reset on a system reset, soft reset,
POR, and the peripheral-specific reset, if applicable.
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