MAX32665-MAX32668 User Guide
Maxim Integrated Page 135 of 457
7.2.1 Clock Configuration
The Flash Controller requires a 1MHz peripheral clock for operation. The input clock to the Flash Controller block is the
system clock,
Use the Flash Controller clock divisor to generate
, as shown in Equation 7-1 below.
For the 96MHz Oscillator as the system clock, the FLCn_CLKDIV.clkdiv should be set to 96 (0x60).
Equation 7-1: Flash Controller Clock Frequency
7.2.2 Lock Protection
A locking mechanism prevents accidental memory writes and erases. All writes and erase operations require the
FLCn_CTRL.unlock field be set to 0x2 prior to starting the operation. Writing any other value to this field, FLCn_CTRL.unlock,
results in:
1) The flash instance remaining locked,
or,
2) The flash instance becoming locked from the unlocked state.
Note: If a write, page erase or mass erase operation is started and the unlock code was not set to 0x2, the flash controller
hardware sets the access fail flag, FLCn_INTR.access_fail, to indicate an access violation occurred.
7.2.3 Flash Write Width
Each Flash Controller supports write widths of 128-bits only. The target address bits FLCn_ADDR[3:0] are ignored resulting
in 128-bit alignment.
Table 7-2: Valid Addresses Flash Writes
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