Maxim Integrated MAX32665 - Power-Down Sequence; Comparator Operation

MAX32665-MAX32668 User Guide
Maxim Integrated Page 254 of 457
Complete the following steps to enable a high and low limit for an ADC input channel using the ADC_LIMIT0 register.
Perform these steps after the ADC is configured for measurement, and the configuration is identical for all four limit
registers except for the limit register name:
1. Verify the ADC is not actively taking a measurement by checking ADC_STATUS.active until it reads 0.
2. Set ADC_LIMIT0.ch_sel field to the selected channel for the high and low limit.
3. Set the high limit, ADC_LIMIT0.ch_hi_limit, to the selected 10-bit trip point. When enabled, an ADC measurement
greater than this field on the channel selected (ADC_LIMIT0.ch_sel) generates an ADC interrupt.
4. Set the low limit, ADC_LIMIT0.ch_lo_limit, to the selected 10-bit low trip point. When enabled, an ADC
measurement lower than this field on the channel selected (ADC_LIMIT0.ch_sel) generates an ADC interrupt.
5. Enable the high limit, the low limit, or both interrupt signals by writing a 1 to ADC_LIMIT0.ch_high_limit_en,
ADC_LIMIT0.ch_low_limit_en, or both. Note: Each limit register is independently enabled for high- and low-limit
interrupts.
6. Clear the ADC interrupt high and low interrupt flags by writing 1 to ADC_INTR.hi_limit_if and
ADC_LIMIT0.lo_limit_if.
7. Enable the high, low, or both interrupts for the ADC by setting ADC_INTR.hi_limit_if to 1, ADC_INTR.lo_limit_ie to
1, or both.
8. If an ADC conversion occurs that is above or below the enabled limits, an ADC_IRQ is generated with the
ADC_LIMIT0.adc_high_limit_if, ADC_LIMIT0.adc_low_limit_if, or both set to 1. The ADC_CTRL.ch_sel value
indicates the channel that caused the interrupt, and the value of the ADC conversion that is out of bounds is in the
ADC_DATA.data field.
11.7.6 Power-Down Sequence
Complete the following steps to power-down the ADC:
1. Set ADC_CTRL.pwr to 0, disabling the ADC converter power.
2. ADC_CTRL.refbuf_pwr to 0, disabling the internal reference buffer power.
3. Set ADC_CTRL.chargepump_pwr to 0, disabling the ADC charge pump.
4. Set ADC_CTRL.clk_en to 0, disabling the ADC internal clock.
11.8 Comparator Operation
Each comparator is individually enabled using MCR_AINCOMP.aincompnpd. When the inputs to any comparator cross their
bias potential, the corresponding flag bit in the PWRSEQ_LPPWST register will be set. Should the user desire, an interrupt
can be generated by setting the corresponding bit in the PWRSEQ_LPPWEN register. The interrupts must be globally
enabled by setting the GCR_PMR.compwken bit.