Maxim Integrated MAX32665 - Table 12-13: UART Transmit FIFO Data Output Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 271 of 457
UART DMA Configuration Register
UARTn_DMA
[0x0020]
Bits
Field
Access
Reset
Description
21:16
rxdma_lvl
R/W
0
Receive FIFO Level DMA Trigger
If the Receive FIFO level is greater than this value, the DMA channel transfers
data from the Receive FIFO. DMA transfers continue until the Receive FIFO is
empty. To avoid an Receive FIFO overrun, do not set this value to 32.
Values above 32 are reserved for future use.
15:14
-
R/W
0
Reserved for Future Use
Do not modify this field.
13:8
txdma_lvl
R/W
0
Transmit FIFO Level DMA Trigger
If the Transmit FIFO level is less than this value, the DMA channel transfers data
into the Transmit FIFO. DMA transfers continue until the Transmit FIFO is full. To
avoid stalling a UART transmission, do not set this value to 1 or 0.
Note: Values above 32 are Reserved for Future Use.
7:6
-
R/W
0
Reserved for Future Use
Do not modify this field.
5
rxdma_auto_to
Receive DMA Timeout Start
If UARTn_CTRL0.to_cnt causes an RX timeout and UARTn_STAT.rx_num is greater
than zero, the DMA transfer will start. Auto-clear after set.
0: Start not initiated.
1: Start DMA transfer.
4
-
R/W
0
Reserved for Future Use
Do not modify this field.
3
rxdma_start
R/W1
0
Receive DMA Start
Regardless of the setting of UARTn_DMA.rxdma_lvl, start the DMA transfer if
UARTn_STAT.rx_num is greater than zero. Auto-clear after set.
0: Start not initiated.
1: Start DMA transfer.
2
-
R/W
0
Reserved for Future Use
Do not modify this field.
1
rxdma_en
R/W
0
Receive FIFO DMA Channel Enable
0: Disabled.
1: Enabled.
0
txdma_en
R/W
0
Transmit FIFO DMA Channel Enable
0: Disabled.
1: Enabled.
Table 12-13: UART Transmit FIFO Data Output Register
UART Transmit FIFO Register
UARTn_TXFIFO
[0x0024]
Bits
Field
Access
Reset
Description
31:8
-
R/W
0
Reserved for Future Use
Do not modify this field.
7:0
data
RO
0
Transmit FIFO Peek Register
Reads from this register return the next character available for transmission at the
end of the Transmit FIFO. If no data is available, reads of this field return 0.
Reads from this register do not affect the Transmit FIFO state.