MAX32665-MAX32668 User Guide
Maxim Integrated Page 280 of 457
In 7-bit addressing mode, the master sends one address byte. To address a 7-bit address slave, first clear
I2Cn_MSTR_MODE.sea= 0, then write the address to the TX FIFO formatted as follows where An is address A6:A0.
Master Writing to Slave : 7-bit address : [A6 A5 A4 A3 A2 A1 A0 0]
Master Reading from Slave : 7-bit address : [A6 A5 A4 A3 A2 A1 A0 1]
In 10-bit addressing mode (I2Cn_MSTR_MODE.sea = 1), the first byte the master sends is the 10-bit Slave Addressing byte
which includes the first two bits of the 10-bit address, followed by a 0 for the R/W bit. That is followed by a second byte
representing the remainder of the 10-bit address. If the operation is a write, this is followed by data bytes to be written to
the slave. If the operation is a read, it is followed by a repeated START. Firmware then writes the 10-bit address again with a
1 for the R/W bit. This I
2
C then starts receiving data from the slave device.
13.4.6 I
2
C Master Mode Operation
The peripheral operates in master mode when Master Mode Enable I2Cn_CTRL0.mst=1. To initiate a transfer, the master
generates a START condition by setting I2Cn_MSTR_MODE.start=1. If the bus is busy, it does not generate a START
condition until the bus is available.
A master can communicate with multiple slave devices without relinquishing the bus. Instead of generating a STOP
condition after communicating with the first slave, the master generates a Repeated START condition, or RESTART, by
setting I2Cn_MSTR_MODE.restart=1. If a transaction is in progress, the peripheral finishes the transaction before generating
a RESTART. The peripheral then transmits the slave address stored in the TX FIFO. The I2Cn_MSTR_MODE.restart bit is
automatically cleared to 0 as soon as the master begins a RESTART condition.
I2Cn_MSTR_MODE.start is automatically cleared to 0 after the master has completed a transaction and sent a STOP
condition.
The master can also generate a STOP condition by setting I2Cn_MSTR_MODE.stop=1.
If both START and RESTART conditions are enabled at the same time, a START condition is generated first. Then, at the end
of the first transaction, a RESTART condition is generated.
If both RESTART and STOP conditions are enabled at the same time, a STOP condition is not generated. Instead, a RESTART
condition is generated. After the RESTART condition is generated, both bits are cleared.
If START, RESTART, and STOP are all enabled at the same time, a START condition is first generated. At the end of the first
transaction, a RESTART condition is generated. The I2Cn_MSTR_MODE.stop bit is cleared and ignored.
A slave cannot generate START, RESTART, or STOP conditions. Therefore, when Master Mode is disabled, the
I2Cn_MSTR_MODE.start, I2Cn_MSTR_MODE.restart, and I2Cn_MSTR_MODE.stop bits are all cleared to 0.
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