MAX32665-MAX32668 User Guide
Maxim Integrated Page 281 of 457
For master mode operation, the following registers should only be configured when either 1) the I
2
C peripheral disabled, or
2) the I
2
C bus is guaranteed to be idle/free. If this peripheral is the only master on the bus, then changing the registers
outside of a transaction (I2Cn_MSTR_MODE.start = 0) will satisfy this requirement:
• I2Cn_CTRL0.mst
• I2Cn_CTRL0.irxm
• I2Cn_CTRL0.scl_ppm
• I2Cn_CTRL0.hsmode
• I2Cn_RX_CTRL1.rxcnt
• I2Cn_MSTR_MODE.sea
• I2Cn_MSTR_MODE.mcode
• I2Cn_CLK_LO.scl_lo
• I2Cn_CLK_HI.scl_hi
• I2Cn_HS_CLK.hs_clk_lo
• I2Cn_HS_CLK.hs_clk_hi
In contrast to the above set of registers, these registers below can be safely (re)programmed at any time:
• All interrupt flags and interrupt enables
• I2Cn_TX_CTRL0.txth
• I2Cn_RX_CTRL0.rxth
• I2Cn_TIMEOUT.to
• I2Cn_DMA.rxen
• I2Cn_DMA.txen
• I2Cn_FIFO.data
• I2Cn_MSTR_MODE.start
• I2Cn_MSTR_MODE.restart
• I2Cn_MSTR_MODE.stop
13.4.6.1 I
2
C Master Mode Receiver Operation
When in Master Mode, initiating a Master Receiver operation begins with the following sequence:
1. Write the number of data bytes to receive to the I
2
C Receive Count field (I2Cn_RX_CTRL1.rxcnt).
2. Write the I
2
C Slave Address Byte to the I2Cn_FIFO register with the R/W bit set to 1
3. Send a START condition by setting I2Cn_MSTR_MODE.start = 1
4. The slave address is transmitted by the controller from the I2Cn_FIFO register.
5. The I
2
C controller receives an ACK from the slave and the controller sets the address ACK interrupt flag
(I2Cn_INT_FL0.adracki = 1).
6. The I
2
C controller receives data from the slave and automatically ACKs each byte. Firmware must retrieve this data
by reading the I2Cn_FIFO register.
7. Once I2Cn_RX_CTRL1.rxcnt data bytes have been received, the I
2
C controller sends a NACK to the slave and sets
the Transfer Done Interrupt Status Flag (I2Cn_INT_FL0.donei = 1).
8. If I2Cn_MSTR_MODE.restart or I2Cn_MSTR_MODE.stop is set, then the I
2
C controller sends a repeated START or
STOP, respectively.