MAX32665-MAX32668 User Guide
Maxim Integrated Page 383 of 457
period of one PCLK cycle. Non-consecutive writes to WDTn_RST.wdt_rst will not cause a reset of the WDT. Attempts to
modify WDTn_CTRL.wdt_en after the one PCLK cycle window will be ignored.
1. Write WDTn_RST.wdt_rst: 0x000000A5
2. Write WDTn_RST.wdt_rst: 0x0000005A
19.5 Enabling the Watchdog Timer
The watchdog timers are free running and require a protected sequence of writes to enable the watchdog timers to prevent
an unintended reset during the enable process.
19.5.1 Enable sequence
1. Write WDTn_RST.wdt_rst: 0x000000A5
2. Write WDTn_RST.wdt_rst: 0x0000005A
3. Set WDTn_CTRL.wdt_en to 1
19.6 Disabling the Watchdog Timer
The watchdog timers can be disabled by software manually or by the microcontroller automatically as shown below.
19.6.1 Manual Disable
Setting WDTn_CTRL.wdt_en to 0 disables the watchdog timer.
19.6.2 Automatic Disable
A power-on-reset (POR) event automatically disables the watchdog timers by setting WDTn_CTRL.wdt_en to 0.
Note: The watchdog timers remain enabled during all other types of reset.
19.7 Resetting the Watchdog Timer
To prevent a WDT interrupt, reset, or both, application software must use the timed-access procedure above to reset the
WDT prior to an interrupt or reset timeout occurring.
19.7.1 Reset Sequence
1. Write WDTn_RST.wdt_rst: 0x000000A5
2. Write WDTn_RST.wdt_rst: 0x0000005A
19.8 Detection of a Watchdog Reset Event
There are multiple hardware and software events that can cause a system reset. If the watchdog timer is being used,
software should check the WDTn_CTRL.rst_flag to determine if the reset was the result of a watchdog reset. Application
software is responsible for taking appropriate actions if a watchdog reset occurred.
19.9 Registers
See Table 3-1: APB Peripheral Base Address Map for the Watchdog Timer’s Peripheral Base Address.
All Watchdog Timer Registers are reset to 0 on a POR and unaffected by other resets.
Table 19-2: Watchdog Timer Register Offsets, Names and Descriptions
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