MAX32665-MAX32668 User Guide
Maxim Integrated Page 236 of 457
Table 9-14: DMA Channel n Destination Register
DMA Channel n Destination
Destination Device Address
For peripheral transfers, the actual address field is either ignored or forced
to zero because peripherals only have one location to read/write data based
on the request select chosen.
If DMACHn_CFG.dstinc = 1, then this register is incremented on every AHB
transfer cycle by one, two, or four bytes depending on the data width.
If a CTZ condition occurs while DMACHn_CFG.rlden = 1, then this register is
reloaded with the contents of the DMAn_DST_RLD register.
Table 9-15: DMA Channel n Count Register
DMA Counter
Load this register with the number of bytes to transfer. This field decreases
on every AHB access to the DMA FIFO. The decrement is one, two, or four
bytes depending on the data width. When the counter reaches 0, a CTZ
condition is triggered.
If a CTZ condition occurs while DMACHn_CFG.rlden = 1, then this register is
reloaded with the contents of the DMAn_CNT_RLD register.
Table 9-16: DMA Channel n Source Reload Register
Source Address Reload Value
If DMACHn_CFG.rlden = 1, then the value of this register is loaded into
DMACHn_SRC upon a CTZ condition.
Table 9-17: DMA Channel n Destination Reload Register
DMA Destination Reload Register
Destination Address Reload Value
If DMACHn_CFG.rlden = 1, then the value of this register is loaded into
DMACHn_DST upon a CTZ condition.
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