MAX32665-MAX32668 User Guide
Maxim Integrated Page 150 of 457
8.2.1.1.7 Slave Select
The SPIXF Master Controller operates with one slave device. A dedicated select pin for slave #0 is provided and controlled
by hardware. Both execute-in-place and data storage are supported on slave #0.
8.2.1.1.8 Interrupts
Interrupt logic is provided to allow efficient servicing of the SPIXF Master Controller by firmware. You can group interrupts
into the following two categories:
• Keeping the Transmit FIFO full
• Keeping the Receive FIFO empty
Programmable levels in the FIFO_CTRL register allow interrupt events to be issued if the Transmit FIFO falls below a certain
level or if the Receive FIFO fills above a certain level. See the FIFO_CTRL register description for more information.
8.2.1.1.9 External SPI Flash Encryption
The user may optionally store encrypted data or code in the external SPI flash. Encryption of the SPI flash data is achieved
using the cryptographic accelerator to encrypt the data and the SPIXF Master Controller to write the data. Data should be
encrypted using AES-128, ECB mode.
Also, the following cryptographic accelerator control bits should be set when encrypting the SPIXF address space:
• CRYPTO_CTRL.bsi
• CRYPTO_CTRL.bso
Setting CRYPTO_CTRL.src = 0b11 selects the key stored for MDIU use in memory locations 0x4000 5080 to 0x4000 508F.
The data must be pre-processed with an address mask. 128 bits plain data blocks are XORed (^) with a 128-bit address mask
to avoid patterns in encrypted data. The address mask, addr_mask below, results in 128-bit aligned addressing by masking
off the lower four bits of the input address (addr_in) as follows:
addr_mask = addr_in & 0xFFFF FFF0
For encryption, the data stored in the SPI flash, data_out below, is calculated as follows:
data_out = AES(data_in ^ ((addr_mask << 96) | ((addr_mask+4) << 64) | \
((addr_mask+8) << 32) | (addr_mask+12)))
where:
data_in = word0:word1:word2:word3 (big endian format)
When using the cryptographic accelerator, the input data should be loaded as follows:
crypto_din0 = word0 ^ (addr_mask)
crypto_din1 = word1 ^ (addr_mask+4)
crypto_din2 = word2 ^ (addr_mask+8)
crypto_din3 = word3 ^ (addr_mask+12)
Once the encrypted data is available (either via FIFO or via Crypto Data Output Registers [3:0]), this data may be written to
SPI flash using the SPIXF Master Controller.
The available output bytes from the cryptographic accelerator should be written to SPIXF flash space as shown in Table 8-3
Table 8-3: Encrypted Data Write Order to SPIX Flash Memory
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