Maxim Integrated MAX32665 - Table 13-15: I C Transmit Control 0 Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 301 of 457
Table 13-15: I
2
C Transmit Control 0 Register
I2C Transmit Control 0
I2Cn_TX_CTRL0
[0x0024]
Bits
Field
Access
Reset
Description
31:12
-
RO
0
Reserved
11:8
txth
R/W
0
TX FIFO Threshold Level
Sets the level for a Transmit FIFO threshold event interrupt. If the number of bytes
remaining in the TX FIFO falls to this level or lower the interrupt flag
I2Cn_INT_FL0.txthi is set indicating a TX FIFO Threshold Event occurred.
0: 0 bytes remaining in the TX FIFO triggers a TX FIFO threshold event.
1: 1 byte or fewer remaining in the TX FIFO triggers a TX FIFO threshold event
(recommended minimum value).
…
7: 7 or fewer bytes remaining in the TX FIFO triggers a TX FIFO threshold event
7
txfsh
R/W1O
0
TX FIFO Flush
A TX FIFO flush clears all remaining data from the transmit FIFO.
0: TX FIFO flush is complete or not active.
1: Flush the TX FIFO
Note: Hardware automatically clears this bit to 0 after it is written to 1 when the
flush is completed.
If I2Cn_INT_FL0.txloi = 1, then I2Cn_TX_CTRL0.txfsh = 1.
6
-
RO
0
Reserved
5
rnacktxafdis
R/W
0
TX FIFO received NACK Auto Flush Disable
Various situations or conditions are described in this user guide that lead to the
Transmit FIFO being flushed and locked out (I2Cn_INT_FL0.txloi = 1).
0: Received NACK at end of Slave Transmit operation enabled
1: Received NACK at end of Slave Transmit operation disabled.
Note: upon entering TX Preload Mode, hardware will automatically set this bit to 0
Software can subsequently set to any value desired (ie HW does not
continuously force the bitfield to this value).
4
samrtxafdis
R/W
0
TX FIFO Slave Address Match Read Auto Flush Disable
Various situations or conditions are described in this user guide that lead to the
Transmit FIFO being flushed and locked out (I2Cn_INT_FL0.txloi = 1).
0: Enabled.
1: Disabled.
Note: upon entering TX Preload Mode, hardware will automatically set this bit to 1
Software can subsequently set to any value desired (ie HW does not
continuously force the bitfield to this value).
3
samwtxafdis
R/W
0
TX FIFO Slave Address Match Write Auto Flush Disable
Various situations or conditions are described in this user guide that lead to the
Transmit FIFO being flushed and locked out (I2Cn_INT_FL0.txloi = 1).
0: Enabled
1: Disabled.
Note: upon entering TX Preload Mode, hardware will automatically set this bit to 1
Software can subsequently set to any value desired (ie HW does not
continuously force the bitfield to this value).