Maxim Integrated MAX32665 - USBHS Device Registers; Table 21-5: USBHS Device Register Offsets, Names, Access, and Descriptions

MAX32665-MAX32668 User Guide
Maxim Integrated Page 409 of 457
Isochronous OUT Endpoint Option
Description
Error Handling – High Bandwidth
Isochronous OUT Endpoints Only
High-bandwidth Isochronous OUT endpoints can transfer three 1024-byte packets in one payload.
To the USB bus, it appears to be a single packet of 3072 bytes. If a high-bandwidth isochronous
data transmission is split into more than one packet, but if less than the expected number of
packets is received by the OUT endpoint, an error condition exists. In this case, the Incomplete
Isochronous Packet Received Error Status bit USBHS_OUTCSRU.incomprx is automatically set to
indicate that the data received in the OUT FIFO is incomplete.
If a packet of the wrong data type is received during a high-bandwidth Isochronous OUT
transaction, then the PID Error Status bit USBHS_OUTCSRU.piderror is automatically set.
21.11 USBHS Device Registers
See Table 3-1: APB Peripheral Base Address Map for the USBHS Peripheral Base Address.
Table 21-5: USBHS Device Register Offsets, Names, Access, and Descriptions
Offset
Register Name
Access
Description
[0x0000]
USBHS_FADDR
R/W
USBHS Device Address Register
[0x0001]
USBHS_POWER
R/W
USBHS Power Management Register
[0x0002]
USBHS_INTRINFL
RO
USBHS IN Endpoint Interrupt Status Register
[0x0004]
USBHS_INTROUTFL
RO
USBHS OUT Endpoint Interrupt Status Flags Register
[0x0006]
USBHS_INTRINEN
R/W
USBHS IN Endpoint Interrupt Enable Register
[0x0008]
USBHS_INTROUTEN
R/W
USBHS OUT Endpoint Interrupt Enable Register
[0x000A]
USBHS_INTSIGFL
RO
USBHS Signaling Interrupt Status Flags Register
[0x000B]
USBHS_INTSIGEN
R/W
USBHS Signaling Interrupt Enable Register
[0x000C]
USBHS_FRAME
RO
USBHS Frame Number Register
[0x000E]
USBHS_INDEX
R/W
USBHS Endpoint and Status Register Index Register
[0x000F]
USBHS_TESTMODE
R/W
USBHS Test Mode Register
[0x0010]
USBHS_INMAXP
R/W
USBHS IN Endpoint Maximum Packet Size Register
[0x0012]
USBHS_CSR0
R/W
USBHS Endpoint 0 Control Status Register (USBHS_INDEX = 0)
[0x0012]
USBHS_INCSRL
R/W
USBHS IN Endpoint Lower Control and Status Register (USBHS_INDEX != 0)
[0x0013]
USBHS_INCSRU
R/W
USBHS IN Endpoint Upper Control and Status Register
[0x0014]
USBHS_OUTMAXP
R/W
USBHS OUT Endpoint Maximum Packet Sizes Register
[0x0016]
USBHS_OUTCSRL
R/W
USBHS OUT Endpoint Lower Control Status Register
[0x0017]
USBHS_OUTCSRU
R/W
USBHS OUT Endpoint Upper Control Status Register
[0x0018]
USBHS_COUNT0
RO
USBHS Endpoint 0 IN FIFO Byte Count Register
[0x0018]
USBHS_OUTCOUNT
RO
USBHS Endpoint OUT FIFO Byte Count Register
[0x0020]
USBHS_FIFO0
R/W
USBHS FIFO for Endpoint 0 Register
[0x0024]
USBHS_FIFO1
R/W
USBHS FIFO for Endpoint 1 Register
[0x0028]
USBHS_FIFO2
R/W
USBHS FIFO for Endpoint 2 Register
[0x002C]
USBHS_FIFO3
R/W
USBHS FIFO for Endpoint 3 Register
[0x0030]
USBHS_FIFO4
R/W
USB HS FIFO for Endpoint 4 Register
[0x0034]
USBHS_FIFO5
R/W
USBHS FIFO for Endpoint 5 Register
[0x0038]
USBHS_FIFO6
R/W
USBHS FIFO for Endpoint 6 Register
[0x003C]
USBHS_FIFO7
R/W
USBHS FIFO for Endpoint 7 Register
[0x0040]
USBHS_FIFO8
R/W
USBHS FIFO for Endpoint 8 Register
[0x0044]
USBHS_FIFO9
R/W
USBHS FIFO for Endpoint 9 Register
[0x0048]
USBHS_FIFO10
R/W
USBHS FIFO for Endpoint 10 Register
[0x004C]
USBHS_FIFO11
R/W
USBHS FIFO for Endpoint 11 Register
[0x0078]
USBHS_EPINFO
RO
USBHS Endpoint Count Info Register
[0x0079]
USBHS_RAMINFO
RO
USBHS RAM and MAInfo Register
[0x007A]
USBHS_SOFTRESET
R/W1C
USBHS Soft Reset Control Register