Maxim Integrated MAX32665 - Table 8-80: SDHC Error Interrupt Signal Enable Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 210 of 457
Normal Interrupt Signal Enable Register
SDHC_INT_SIGNAL
[0x0038]
Bits
Name
Access
Reset
Description
6
card_insert
R/W
0
Card Insertion Signal Enable
1: Enabled
0: Disabled
5
buffer_rd
R/W
0
Buffer Read Ready Signal Enable
1: Enabled
0: Disabled
4
buffer_wr
R/W
0
Buffer Write Ready Signal Enable
1: Enabled
0: Disabled
3
dma
R/W
0
DMA Interrupt Signal Enable
1: Enabled
0: Disabled
2
blk_gap
R/W
0
Block Gap Signal Enable
1: Enabled
0: Disabled
1
trans_comp
R/W
0
Transfer Complete Signal Enable
1: Enabled
0: Disabled
0
cmd_comp
R/W
0
Command Complete Signal Enable
1: Enabled
0: Disabled
Table 8-80: SDHC Error Interrupt Signal Enable Register
Error Interrupt Signal Enable Register
SDHC_ER_INT_SIGNAL
[0x003A]
Bits
Name
Access
Reset
Description
15:13
-
R/W
0
Reserved for Future Use
Do not modify this field.
12
tar_resp
R/W
0
Target Response Error Signal Enable
1: Enabled
0: Disabled
11
-
R/W
0
Reserved for Future Use
Do not modify this field.
10
tuning
R/W
0
Tuning Error Signal Enable
1: Enabled
0: Disabled
9
adma
R/W
0
ADMA Error Signal Enable
1: Enabled
0: Disabled
8
auto_cmd_12
R/W
0
Auto CMD12 Error Signal Enable
1: Enabled
0: Disabled
7
current_limit
R/W
0
Current Limit Error Signal Enable
1: Enabled
0: Disabled