MAX32665-MAX32668 User Guide
Maxim Integrated Page 382 of 457
As soon as possible after a reset, the application software should interrogate the WDTn_CTRL.rst_flag to determine if the
reset event resulted from a watchdog timer reset. If so, application software should assume that there was a program
execution error and take whatever steps necessary to guard against a software corruption issue.
19.3 Interrupt and Reset Period Timeout Configuration
Each watchdog timer supports two independent timeout periods, the interrupt period timeout and reset period timeout.
• Interrupt Period Timeout: WDTn_CTRL.int_period sets the number of PCLK cycles until a watchdog timer interrupt
is generated. This period must be less than the Reset Period Timeout for the watchdog timer interrupt to occur.
• Reset Period Timeout: WDTn_CTRL.rst_period sets the number of PCLK cycles until a system reset event occurs.
The interrupt and reset period timeouts are calculated using Equation 19-1 and Equation 19-2 respectively, where
. Table 19-1 shows example interrupt period timeout values.
Equation 19-1: Watchdog Timer Interrupt Period
Equation 19-2. Watchdog Timer Reset Period
Table 19-1: Watchdog Timer Interrupt Period fSYS_CLK = 96MHz and fPCLK = 48MHz
19.4 Timed Access Protection
The WDT is a critical system safeguard, and is protected against accidental accesses that would enable, disable, or reset the
watchdog timer.
The timed-access protection requires software to write two specific values to the timed-access register WDTn_RST.wdt_rst
during consecutive instruction cycles. This simultaneously resets the WDT and unlocks access to WDTn_CTRL.wdt_en for a
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