MAX32665-MAX32668 User Guide
Maxim Integrated Page 446 of 457
Cryptographic Control Register
Write FIFO Source Select
This field determines the source of the write FIFO data.
0b00: None
0b01: Cipher Output
0b10: Read FIFO
0b11: Reserved
Wait Pin Polarity
This feature is not implemented in this device. Do not change this bit from its default
value.
0: Active low
1: Active high
Wait Pin Enable
This feature is not implemented in this device. Do not change this bit from its default
value.
0: Disabled
1: Enabled. CMDA will be halted when the pin is in its active state.
Byte Swap Input
Note: No byte swap occurs if there is not a full word.
0: No effect.
1: Byte swap input.
Byte Swap Output
Note: No byte swap occurs if there is not a full word.
0: No effect.
1: Byte swap output.
Reserved for Future Use
Do not modify this field from its default value.
Source Select
This bit selects the hash function and CRC generator input source.
0: Input FIFO
1: Output FIFO
Interrupt Enable
Generates an interrupt when done or error set.
0: Interrupt disabled
1: Interrupt asserted when CRYPTO_CTRL.done is set.
Reset Cryptographic Accelerator
Setting this bit initiates an internal reset of the cryptographic accelerator. Software
must poll the CRYPTO_CTRL.rdy bit to determine when the reset process is complete.
All cryptographic internal states and related registers are reset to their default reset
values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRLCRC_CTRL,,
MAA_CTRL (with the exception of the STC bit). HASH MSG_SZ_3:0, and MAA_MAWS
retain their values. This bit automatically clears itself after one cycle.
0: No effect
1: Reset cryptographic accelerator
Table 23-9: Cipher Control Register
Reserved for Future Use
Do not modify this field from its default value.