Maxim Integrated MAX32665 - Table 8-84: SDHC Capabilities Register 1

MAX32665-MAX32668 User Guide
Maxim Integrated Page 215 of 457
Table 8-84: SDHC Capabilities Register 1
Capabilities Register 1
SDHC_CFG_1
[0x0044]
Bits
Name
Access
Reset
Description
31:24
-
RO
1
Reserved for Future Use
Do not modify this field.
23:16
clk_multi
RO
0
Clock Multiplier
Always reads 0x00.
0: Programmable clock generation is not supported.
15:14
retuning
RO
0
Re-Tuning Modes
Always reads 0b00. The SDHC supports Mode 1 Re-Tuning only with timer
controlled by the host driver and a maximum of 4MB data length.
13
tuning_sdr50
RO
0
Use Tuning for SDR50
1: Tuning required for SDR50
0: SDR50 does not require tuning
12
-
RO
0
Reserved for Future Use
Do not modify this field.
11:8
timer_cnt_tuning
RO
0
Timer Count for Re-Tuning
0x0: Re-Tuning Timer disabled
0x1: 1 second
0x2: 2 seconds
0x3: 4 seconds
0x4: 8 seconds
….: …………
n: 
󰇛

󰇜

….: …………
0xB: 1024 seconds
0xC: Reserved
0xD: Reserved
0xE: Reserved
0xF: Get information from another source
7
-
RO
0
Reserved for Future Use
Do not modify this field.
6
driver_d
RO
1
Driver Type D Support
1: Driver Type D is supported
5
driver_c
RO
1
Driver Type C Support
1: Driver Type C is supported
4
driver_a
RO
1
Driver Type A Support
1: Driver Type A is supported
3
-
RO
0
Reserved for Future Use
Do not modify this field.
2
ddr50
RO
1
DDR50 Support
1: DDR50 is support
1
sdr104
RO
1
SRD104
1: SDR104 is supported
0
sdr50
RO
1
SDR50
1: SDR50 is supported