Maxim Integrated MAX32665 - Page 214

MAX32665-MAX32668 User Guide
Maxim Integrated Page 214 of 457
Capabilities Register 0
SDHC_CFG_0
[0x0040]
Bits
Name
Access
Reset
Description
27
-
RO
0
Reserved for Future Use
26
1_8v
RO
1
Voltage Support 1.8V
1: 1.8V supported
25
3_0v
RP
1
Voltage Support 3.0V
1: 3.0V supported
24
3_3v
RO
1
Voltage Support 3.3V
1: 3.3V supported
23
suspend
RO
1
Suspend/Resume Support
1: Suspend / Resume functionality is supported
22
sdma
RO
1
SDMA Support
SDMA is supported and can transfer data between system memory and the
SDHC directly.
1: SDMA supported
21
hs
RO
1
High Speed Support
The SDHC supports High Speed mode with f
PCLK
=96MHz/2.
1: High speed mode supported
20
-
RO
0
Reserved for Future Use
Do not modify this field.
19
adma2
RO
1
ADMA2 Support
The SDHC supports ADMA2.
1: ADMA2 supported
18
8_bit
RO
0
8-bit Support for Embedded Device
The SDHC supports 8-bit bus width mode.
0: 8-bit Bus width not supported
17:16
max_blk_len
RO
0b10
Max Block Length
This value indicates the maximum block size that the Host Driver can read and
write to the buffer in the SDHC without wait cycles. The transfer block length is
always 512 bytes for SD memory cards regardless of this field.
0b10: 2048 bytes
15:8
clk_freq
RO
0x00
Base Clock Frequency for SD Clock
0x00: Get information using another method
7
clk_unit
RO
1
Timeout Clock Unit
1: MHz base clock unit
6
-
RO
0
Reserved for Future Use
Do not modify this field.
5:0
clk_freq
RO
0x01
Timeout Clock Frequency
The base clock frequency used to detect Data Timeout errors. The Timeout
Clock Unit defines the units of this field’s value.
1: 1 [MHz]