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Maxim Integrated MAX32665 - Register Details; Table 12-3: UART Register Summary; Table 12-4: UART Control 0 Register

Maxim Integrated MAX32665
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MAX32665-MAX32668 User Guide
Maxim Integrated Page 264 of 457
Table 12-3: UART Register Summary
Offset
Name
Description
[0x0000]
UARTn_CTRL0
UARTn Control 0 Register
[0x0004]
UARTn_CTRL1
UARTn Control 1 Register
[0x0008]
UARTn_STAT
UARTn Status Register
[0x000C]
UARTn_INT_EN
UARTn Interrupt Enable Register
[0x0010]
UARTn_INT_FL
UARTn Interrupt Flag Register
[0x0014]
UARTn_BAUD0
UARTn Baud Rate Integer Register
[0x0018]
UARTn_BAUD1
UARTn Baud Rate Decimal Register
[0x001C]
UARTn_FIFO
UARTn FIFO Read/Write Register
[0x0020]
UARTn_DMA
UARTn DMA Configuration Register
[0x0024]
UARTn_TXFIFO
UARTn Transmit FIFO Register
12.10 Register Details
Table 12-4: UART Control 0 Register
UART Control 0
UARTn_CTRL0
[0x0000]
Bits
Field
Access
Reset
Description
31:24
-
R/W
0
Reserved for Future Use
Do not modify this field.
23:16
to_cnt
R/W
0
Receive Timeout Frame Count
Represents the number of frames to wait for a character. If the Receive FIFO contains
data, a Receive Timeout condition occurs if the number of frames in this register
passes without the FIFO receiving any new data. If a timeout occurs, the hardware sets
the receive timeout flag to 1 (UARTn_INT_FL.rx_to = 1).
15
clk_sel
R/W
0
Bit Rate Clock Source Select
0:


1:

.
14
break
R/W
0
Transmit BREAK
Set this field to 1 to set the TX line low during a character transmission. A character
must be transmitting for this feature to operate. The Tx line remains low until this field
is set to zero.
0: Normal UART operation.
1: Transmit zero during a character transfer.
13
nullmod
R/W
0
Null Modem Support
0: Normal operation for RTS/CTS and TX/RX
1: Null Modem Mode: RTS/CTS swapped, TX/RX swapped
12
flowpol
R/W
0
RTS/CTS Polarity
This field controls the polarity used for the RTS/CTS signals. Setting this field to 0
indicates active low assertion for the signals. Setting this field to 1 uses an active high
assertion.
0: RTS/CTS asserted is 0
1: RTS/CTS asserted is 1
11
flowctl
R/W
0
Hardware Flow Control Enable
0: Hardware flow control disabled.
1: Hardware RTS/CTS flow control enabled.

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