Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
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13.3 I
2
C Overview
13.3.1 I
2
C Bus Terminology
Table 13-2, below, contains terms and definitions used in this chapter for the I
2
C Bus Terminology.
Table 13-2: I
2
C Bus Terminology
Term
Definition
Transmitter
The device that sends data to the bus.
Receiver
The device that receives data from the bus.
Master
The device that initiates a transfer, generates clock signals and terminates a transfer.
Slave
The device addressed by a master.
Multi-master
More than one master can attempt to control the bus at the same time without corrupting the message.
Arbitration
Procedure to ensure that, if more than one master simultaneously tries to control the bus, only one can do
so and the resulting message is not corrupted.
Synchronization
Procedure to synchronize the clock signals of two or more devices.
Clock Stretching
When a slave device holds SCL low to pause a transfer until it is ready. This feature is optional according to
the I
2
C Specification; thus, a master does not have to support slave clock stretching if none of the slaves in
the system are capable of clock stretching.
13.3.2 I
2
C Transfer Protocol Operation
The I
2
C protocol operates over a two-wire bus: a clock circuit (SCL) and a data circuit (SDA). I
2
C is a half-duplex protocol:
only one device is allowed to transmit on the bus at a time.
Each transfer is initiated when the bus master sends a START or repeated START condition. It is followed by the I
2
C slave
address of the targeted slave device plus a read/write bit. The master can transmit data to the slave (a ‘write’ operation) or
receive data from the slave (a ‘read’ operation). Information is sent most significant bit (MSB) first. Following the slave
address, the master indicates a read or write operation and then exchanges data with the addressed slave. An acknowledge
bit is sent by the receiving device after each byte is transferred. When all necessary data bytes have been transferred, a
STOP or RESTART condition is sent by the bus master to indicate the end of the transaction. After the STOP condition has
been sent, the bus is idle and ready for the next transaction. After a RESTART condition is sent, the same master begins a
new transmission. The number of bytes that can be transmitted per transfer is unrestricted.
13.3.3 START and STOP Conditions
A START condition occurs when a bus master pulls SDA from high to low while SCL is high, and a STOP condition occurs
when a bus master allows SDA to be pulled from low to high while SCL is high. Because these are unique conditions that
cannot occur during normal data transfer, they are used to denote the beginning and end of the data transfer.
13.3.4 Master Operation
I
2
C transmit and receive data transfer operations occur through the I2Cn_FIFO register. Writes to the register load the TX
FIFO and reads of the register return data from the RX FIFO. If a slave sends a NACK in response to a write operation, the
I2C master generates an interrupt. The I2C controller can be configured to issue a STOP condition to free the bus.
The receive FIFO contains the received data. If the receive FIFO is full or the transmit FIFO is empty, the I2C master stops
the clock to allow time to read bytes from the receive FIFO or load bytes into the transmit FIFO.
13.3.5 Acknowledge and Not Acknowledge
An acknowledge bit (ACK) is generated by the receiver, whether I
2
C master or slave, after every byte received by pulling
SDA low. The ACK bit is how the receiver tells the transmitter that the byte was successfully received, and another byte
might be sent.
A Not Acknowledge (NACK) occurs if the receiver does not generate an ACK when the transmitter releases SDA. A NACK is
generated by allowing SDA to float high during the acknowledge time slot. The I
2
C master can then either generate a STOP

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English