Maxim Integrated MAX32665 - Mass Erase; Flash Error Correction Coding; Flash Controller Registers; Table 7-3: Flash Controller Registers

MAX32665-MAX32668 User Guide
Maxim Integrated Page 137 of 457
7.2.6 Mass Erase
CAUTION: Care must be taken to not erase the flash from which application code is currently executing.
Mass erase clears the internal flash memory on an instance basis. Perform the following steps to mass erase a single flash
memory instance:
1. Read the FLCn_CTRL.busy bit until it returns 0.
2. Configure FLCn_CLKDIV.clkdiv to match the SYS_CLK frequency.
3. Set FLCn_CTRL.unlock to 0x2 to unlock the internal flash.
4. Set FLCn_CTRL.erase_code to 0xAA for mass erase.
5. Set FLCn_CTRL.mass_erase to 1 to start the mass erase operation.
6. The FLCn_CTRL.busy bit is set by the flash controller while the mass erase is in progress and the
FLCn_CTRL.mass_erase and FLCn_CTRL.busy are cleared by the flash controller when the mass erase is complete.
7. FLCn_INTR.done is set by the flash controller when the mass erase completes and if an error occurred, the
FLCn_INTR.access_fail flag is set. These bits generate a flash IRQ if the interrupt enable bits are set.
8. Set FLCn_CTRL.unlock to any value other than 0x2 to re-lock the flash instance.
7.3 Flash Error Correction Coding
The Flash Controller ECC data register FLCn_ECC_Data stores the ECC bits from the last flash instance read memory
location. The register contains 9 bits of ECC data of the even 128-bit flash memory location FLCn_ECC_Data.ecc_even and 9
bits of ECC data of the 128-bit odd flash memory location FLCn_ECC_Data.ecc_odd. These 9-bit ECC data fields are dynamic
and are valid only immediately after each location read and represent the ECC for 256 bits of flash. The 128-bit even
location of this even/odd pair is matched with the 128-bit odd location of the lower-valued memory address. In case of ECC
error from internal flash memory read cycles, the FLCn_ECC_Data can be used in conjunction with the Table 4-70: Error
Correction Coding Interrupt Enable Register to debug the ECC failure.
7.4 Flash Controller Registers
See Table 3-1: APB Peripheral Base Address Map for the Flash Controller 0 and Flash Controller 1 Peripheral Base Addresses.
Table 7-3: Flash Controller Registers
Offset
Register Name
Access
Description
[0x0000]
FLCn_ADDR
R/W
Flash Controller Address Pointer Register
[0x0004]
FLCn_CLKDIV
R/W
Flash Controller Clock Divisor Register
[0x0008]
FLCn_CTRL
R/W
Flash Controller Control Register
[0x0024]
FLCn_INTR
R/W
Flash Controller Interrupt Register
[0x0028
FLCn_ECC_Data
R/W
Flash Controller Error Correction Code Data
[0x0030]
FLCn_DATA0
R/W
Flash Controller Data Register 0
[0x0034]
FLCn_DATA1
R/W
Flash Controller Data Register 1
[0x0038]
FLCn_DATA2
R/W
Flash Controller Data Register 2
[0x003C]
FLCn_DATA3
R/W
Flash Controller Data Register 3