Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 316 of 457
QSPIn Control 0 Register
QSPIn_CTRL0
[0x0004]
Bits
Name
Access
Reset
Description
4
ss_io
R/W
0
Master Slave Select Signal Direction
Set the I/O direction for
0: Slave Select is an output
1: Slave Select is an input
Note: This field is only used when the QSPIn is configured for Master Mode
(QSPIn_CTRL0.mm_en = 1).
3:2
-
R/W
0
Reserved for Future Use
Do not modify this field.
1
mm_en
R/W
0
SPI Master Mode Enable
This field selects between slave mode and master mode operation for the SPI
port. Write this field to 0 to operate as an SPI slave. Setting this field to 1 sets the
port as an SPI master.
0: Slave mode SPI operation.
1: Master mode SPI operation.
0
enable
R/W
0
SPI Enable/Disable
This field enables and disables the QSPIn port. Disable the QSPIn port by setting
this field to 0. Disabling the QSPIn port does not affect the QSPIn FIFOs or register
settings.
0: QSPIn port is disabled
1: QSPIn port is enabled
Table 14-9: QSPIn Transmit Packet Size Register
QSPIn Transmit Packet Size Register
QSPIn_CTRL1
[0x0008]
Bits
Name
Access
Reset
Description
31:16
rx_num_char
R/W
0
Number of Receive Characters
Number of characters to receive in RX FIFO.
Note: If the QSPIn port is set to operate in 4-wire mode, this field is ignored and
the QSPIn_CTRL1.tx_num_chars field is used for both the number of characters to
receive and transmit.
15:0
tx_num_char
R/W
0
Number of Transmit Characters
Number of characters to transmit from TX FIFO.
Note: If the QSPIn port is set to operate in 4-wire mode, this field is used for both
the number of characters to receive and transmit.
Table 14-10: QSPIn Control 2 Register
QSPIn Control 2 Register
QSPIn_CTRL2
[0x000C]
Bits
Name
Access
Reset
Description
31:20
-
R/W
0
Reserved for Future Use
Do not modify this field.
19:16
ss_pol
R/W
0
Slave Select Polarity
Controls the polarity of each individual SS signal where each bit position
corresponds to a SS signal. QSPIn_SS0 is controlled with bit position 0 and
QSPIn_SS2 is controlled with bit position 2.
For each bit position,
0: SS is active low
1: SS is active high

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English