Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 346 of 457
Table 16-4: Timer Interrupt Registers
Timer Interrupt Register
TMRn_INT
[0x000C]
Bits
Name
Access
Reset
Description
31:1
-
RO
0
Reserved for Future Use
Do not modify this field from its default value.
0
irq
RW
0
Timer Interrupt
If set, this field indicates a timer interrupt condition occurred.
Writing any value to this bit clears the timer’s interrupt.
0: Timer interrupt is not active.
1: Timer interrupt occurred.
Table 16-5: Timer Control Registers
Timer Control Register
TMRn_CN
[0x0010]
Bits
Name
Access
Reset
Description
31:13
-
RO
0
Reserved for Future Use
Do not modify this field from its default value.
12
pwmckbd
R/W
1
PWM Output 

󰆓
Disable
1: Disable PWM Output 

󰆓
0: Enable PWM Output 

󰆓
11
nollpol
R/W
0
PWM Output 

󰆓
Polarity Bit
1: Output 

󰆓
inverted
0: Output 

󰆓
non-inverted
10
nolhpol
R/W
0
PWM Output 

Polarity Bit
1: Output 

inverted
0: Output 

non-inverted
9
pwmsync
R/W
0
PWM Synchronization Mode
1: PWM synchronization mode enabled
0: PWM synchronization mode disabled
8
pres3
R/W
0
Timer Prescale Select MSB
See TMRn_CN.pres for details on this field’s usage.
7
ten
R/W
0
Timer Enable
1: Timer enabled
0: Timer disabled
6
tpol
R/W
0
Timer Polarity
Selects the polarity of the timer’s input and output signal. This setting is not used if
the GPIO is not configured for the alternate function. The tpol field meaning is
determined by the specific mode of the timer. See the mode’s detailed configuration
section for tpol usage.

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English